Registers; General Purpose Registers - Xilinx MicroBlaze Reference Manual

Registers

MicroBlaze has an orthogonal instruction set architecture. It has thirty-two 32-bit general
purpose registers and up to eighteen 32-bit special purpose registers, depending on
configured options.

General Purpose Registers

The thirty-two 32-bit General Purpose Registers are numbered R0 through R31. The register
file is reset on bit stream download (reset value is 0x00000000). The following figure is a
representation of a General Purpose Register and
register and the register reset value (if existing).
The register file is not reset by the external reset inputs: Reset and Debug_Rst.
Note:
X-Ref Target - Figure 2-2
0
Table 2-7: General Purpose Registers (R0-R31)
Bits Name
0:31 R0
0:31 R1 through R13
0:31 R14
0:31 R15
0:31 R16
0:31 R17
0:31 R18 through R31
See Table 4-2 for software conventions on general purpose register usage.
MicroBlaze Processor Reference Guide
UG984 (v2018.2) June 21, 2018
R0 – R31
Figure 2-2: R0-R31
Description
Always has a value of zero. Anything written to R0 is
discarded
32-bit general purpose registers
32-bit register used to store return addresses for
interrupts.
32-bit general purpose register. Recommended for storing
return addresses for user vectors.
32-bit register used to store return addresses for breaks.
If MicroBlaze is configured to support hardware
exceptions, this register is loaded with the address of the
instruction following the instruction causing the HW
exception, except for exceptions in delay slots that use BTR
instead (see Branch Target Register
general purpose register.
R18 through R31 are 32-bit general purpose registers.
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Chapter 2: MicroBlaze Architecture
Table 2-7 provides a description of each
(BTR)); if not, it is a
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31
X19739-091117
Reset Value
0x00000000
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