Xilinx MicroBlaze Reference Manual page 41

Translation Look-Aside Buffer Index Register (TLBX)
The Translation Look-Aside Buffer Index Register is used as an index to the Unified
Translation Look-Aside Buffer (UTLB) when accessing the TLBLO and TLBHI registers. It is
controlled by the
implemented if
0 (Performance) or 2 (Frequency). When accessed with the MFS and MTS instructions, the
TLBX is specified by setting
The following figure illustrates the TLBX register and
and reset values.
X-Ref Target - Figure 2-16
0
MISS
Table 2-22: Translation Look-Aside Buffer Index Register (TLBX)
Bits Name
0 MISS
1:25 Reserved
26:31 INDEX
MicroBlaze Processor Reference Guide
UG984 (v2018.2) June 21, 2018
configuration option on MicroBlaze. The register is only
C_USE_MMU
is greater than 1 (User Mode), and
C_USE_MMU
Sa = 0x1002
Reserved
Figure 2-16: TLBX
TLB Miss
This bit is cleared to 0 when the TLBSX register is written with a
virtual address, and the virtual address is found in a TLB entry.
The bit is set to 1 if the virtual address is not found. It is also cleared
when the TLBX register itself is written.
Read Only
Can be read if the memory management special registers
parameter C_MMU_TLB_ACCESS > 0 (MINIMAL) .
TLB Index
This field is used to index the Translation Look-Aside Buffer entry
accessed by the TLBLO and TLBHI registers. The field is updated
with a TLB index when the TLBSX register is written with a virtual
address, and the virtual address is found in the corresponding TLB
entry.
Read/Write
Can be read and written if the memory management special
registers parameter C_MMU_TLB_ACCESS > 0 (MINIMAL) .
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Chapter 2: MicroBlaze Architecture
C_AREA_OPTIMIZED
.
Table 2-22
Description
is set to
provides bit descriptions
26
INDEX
X19753-082517
Reset Value
0
000000
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31
41