Xilinx MicroBlaze Reference Manual page 254

Latency
• 1 cycle
Notes
To refer to special purpose registers in assembly language, use rpc for PC, rmsr for MSR, rear for EAR,
resr for ESR, rfsr for FSR, rbtr for BTR, redr for EDR, rslr for SLR, rshr for SHR, rpid for PID, rzpr for ZPR,
rtlblo for TLBLO, rtlbhi for TLBHI, rtlbx for TLBX, and rpvr0 - rpvr12 for PVR0 - PVR12.
The value read from MSR might not include effects of the immediately preceding instruction
(dependent on pipeline stall behavior). An instruction that does not affect MSR must precede the MFS
instruction to guarantee correct MSR value.
The value read from FSR might not include effects of the immediately preceding instruction
(dependent on pipeline stall behavior). An instruction that does not affect FSR must precede the MFS
instruction to guarantee correct FSR value.
EAR, ESR and BTR are only valid as operands when at least one of the MicroBlaze C_*_EXCEPTION
parameters are set to 1.
EDR is only valid as operand when the parameter C_FSL_EXCEPTION is set to 1 and the parameter
C_FSL_LINKS is greater than 0.
FSR is only valid as an operand when the C_USE_FPU parameter is greater than 0.
SLR and SHR are only valid as an operand when the C_USE_STACK_PROTECTION parameter is set to
1.
PID, ZPR, TLBLO and TLBHI are only valid as operands when the parameter C_USE_MMU > 1 (User
Mode) and the parameter C_MMU_TLB_ACCESS = 1 (Read) or 3 (Full).
TLBX is only valid as operand when the parameter C_USE_MMU > 1 (User Mode) and the parameter
C_MMU_TLB_ACCESS > 0 (Minimal).
PVR0 is only valid as an operand when C_PVR is 1 (Basic) or 2 (Full), and PVR1 - PVR12 are only valid
as operands when C_PVR is set to 2 (Full).
The extended instruction is only valid if MicroBlaze is configured to use extended address
(C_ADDR_SIZE > 32).
MicroBlaze Processor Reference Guide
UG984 (v2018.2) June 21, 2018
Chapter 5: MicroBlaze Instruction Set Architecture
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