Xilinx MicroBlaze Reference Manual page 140

Table 3-1: Summary of MicroBlaze Core I/O (Cont'd)
Signal
M_AXI_IC_AWLOCK
M_AXI_IC_AWCACHE
M_AXI_IC_AWPROT
M_AXI_IC_AWQOS
M_AXI_IC_AWVALID
M_AXI_IC_AWREADY
M_AXI_IC_AWUSER
M_AXI_IC_AWDOMAIN
M_AXI_IC_AWSNOOP
M_AXI_IC_AWBAR
M_AXI_IC_WDATA
M_AXI_IC_WSTRB
M_AXI_IC_WLAST
M_AXI_IC_WVALID
M_AXI_IC_WREADY
M_AXI_IC_WUSER
M_AXI_IC_BID
M_AXI_IC_BRESP
M_AXI_IC_BVALID
M_AXI_IC_BREADY
M_AXI_IC_BUSER
M_AXI_IC_WACK
M_AXI_IC_ARID
M_AXI_IC_ARADDR
M_AXI_IC_ARLEN
M_AXI_IC_ARSIZE
M_AXI_IC_ARBURST
M_AXI_IC_ARLOCK
M_AXI_IC_ARCACHE
M_AXI_IC_ARPROT
M_AXI_IC_ARQOS
M_AXI_IC_ARVALID
M_AXI_IC_ARREADY
M_AXI_IC_ARUSER
M_AXI_IC_ARDOMAIN
MicroBlaze Processor Reference Guide
UG984 (v2018.2) June 21, 2018
Interface I/O
O Master Lock type
M_AXI_IC
Master Cache type
O
M_AXI_IC
O Master Protection type
M_AXI_IC
O Master Quality of Service
M_AXI_IC
Master Write address valid
O
M_AXI_IC
I Slave Write address ready
M_AXI_IC
O Master Write address user signals
M_AXI_IC
O Master Write address domain
M_ACE_IC
Master Write address snoop
O
M_ACE_IC
O Master Write address barrier
M_ACE_IC
O Master Write data
M_AXI_IC
Master Write strobes
O
M_AXI_IC
O Master Write last
M_AXI_IC
O Master Write valid
M_AXI_IC
I Slave Write ready
M_AXI_IC
Master Write user signals
O
M_AXI_IC
I Slave Response ID
M_AXI_IC
I Slave Write response
M_AXI_IC
I Slave Write response valid
M_AXI_IC
Master Response ready
O
M_AXI_IC
I Slave Write response user signals
M_AXI_IC
O Slave Write acknowledge
M_ACE_IC
Master Read address ID
O
M_AXI_IC
O Master Read address
M_AXI_IC
O Master Burst length
M_AXI_IC
O Master Burst size
M_AXI_IC
Master Burst type
O
M_AXI_IC
O Master Lock type
M_AXI_IC
O Master Cache type
M_AXI_IC
Master Protection type
O
M_AXI_IC
O Master Quality of Service
M_AXI_IC
O Master Read address valid
M_AXI_IC
I Slave Read address ready
M_AXI_IC
Master Read address user signals
O
M_AXI_IC
O Master Read address domain
M_ACE_IC
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Chapter 3: MicroBlaze Signal Interface Description
Description
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