Xilinx MicroBlaze Reference Manual page 246

lhui Load Halfword Unsigned Immediate
rD, rA, IMM
lhui
1 1 1 0 0 1
0
6
Description
Loads a halfword (16 bits) from the halfword aligned memory location that results from adding the
contents of register rA and the value in IMM, sign-extended to 32 bits. The data is placed in the least
significant halfword of register rD and the most significant halfword in rD is cleared.
A data TLB miss exception occurs if virtual protected mode is enabled, and a valid translation entry
corresponding to the address is not found in the TLB. A data storage exception occurs if access is
prevented by a no-access-allowed zone protection. This only applies to accesses with user mode and
virtual protected mode enabled. An unaligned data access exception occurs if the least significant bit
in the address is not zero.
Pseudocode
←
Addr (rA) + sext(IMM)
if TLB_Miss(Addr) and MSR[VM] = 1 then
←
ESR[EC] 10010;ESR[S]
←
MSR[UMS]
else if Access_Protected(Addr) and MSR[UM] = 1 and MSR[VM] = 1 then
←
ESR[EC]
←
MSR[UMS]
else if Addr[31]
←
ESR[EC]
else
(rD)[16:31]
(rD)[0:15]
Registers Altered
• rD, unless an exception is generated, in which case the register is unchanged
• MSR[UM], MSR[VM], MSR[UMS], MSR[VMS], if a TLB miss exception or a data storage
exception is generated
• ESR[EC], ESR[S], if an exception is generated
• ESR[DIZ], if a data storage exception is generated
• ESR[W], ESR[Rx], if an unaligned data access exception is generated
Latency
• 1 cycle with
• 2 cycles with
Note
By default, Type B Instructions will take the 16-bit IMM field value and sign extend it to 32 bits to use
as the immediate operand. This behavior can be overridden by preceding the Type B instruction with
an imm instruction. See the instruction
MicroBlaze Processor Reference Guide
UG984 (v2018.2) June 21, 2018
rD rA
11
←
0
←
MSR[UM]; MSR[VMS]
←
10000;ESR[S] 0; ESR[DIZ]
←
MSR[UM]; MSR[VMS]
≠
0 then
←
00001; ESR[W] 0; ESR[S]
←
Mem(Addr)
←
0
=0 or 2
C_AREA_OPTIMIZED
=1
C_AREA_OPTIMIZED
"imm"
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Chapter 5: MicroBlaze Instruction Set Architecture
16
←
MSR[VM]; MSR[UM] 0; MSR[VM]
←
1
←
MSR[VM]; MSR[UM] 0; MSR[VM]
← ←
0; ESR[Rx]
for details on using 32-bit immediate values.
IMM
←
0
←
0
rD
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