Xilinx MicroBlaze Reference Manual page 9

Table 2-1: Configurable Feature Overview by MicroBlaze Version (Cont'd)
Feature
Disable hardware multiplier
Hardware debug readable ESR and
EAR
Processor Version Register (PVR)
Area or speed optimized
Hardware multiplier 64-bit result
LUT cache memory
Floating-point conversion and
square root instructions
Memory Management Unit (MMU)
Extended stream instructions
Use Cache Interface for All I-Cache
Memory Accesses
Use Cache Interface for All D-Cache
Memory Accesses
Use Write-back Caching Policy for
D-Cache
Branch Target Cache (BTC)
Streams for I-Cache
Victim handling for I-Cache
Victim handling for D-Cache
AXI4 (M_AXI_DP) data side interface
AXI4 (M_AXI_IP) instruction side
interface
AXI4 (M_AXI_DC) protocol for D-
Cache
AXI4 (M_AXI_IC) protocol for I-
Cache
AXI4 protocol for stream accesses
Fault tolerant features
Force distributed RAM for cache
tags
Configurable cache data widths
Count Leading Zeros instruction
Memory Barrier instruction
Stack overflow and underflow
detection
Allow stream instructions in user
mode
MicroBlaze Processor Reference Guide
UG984 (v2018.2) June 21, 2018
v9.2
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Chapter 2: MicroBlaze Architecture
MicroBlaze versions
v9.3 v9.4
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v9.5 v9.6 v10.0
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Send Feedback
Yes
Yes
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