Xilinx MicroBlaze Reference Manual page 174

Table 3-19: Configuration Parameters (Cont'd)
Parameter Name
C_ECC_USE_CE_EXCEPTION
C_LOCKSTEP_SLAVE
C_AVOID_PRIMITIVES
C_ENABLE_DISCRETE_PORTS
C_PVR
C_PVR_USER1
C_PVR_USER2
C_RESET_MSR_IE
C_RESET_MSR_BIP
C_RESET_MSR_ICE
C_RESET_MSR_DCE
C_RESET_MSR_EE
C_RESET_MSR_EIP
C_INSTANCE
C_D_AXI
C_D_LMB
C_I_AXI
C_I_LMB
C_USE_BARREL
MicroBlaze Processor Reference Guide
UG984 (v2018.2) June 21, 2018
Chapter 3: MicroBlaze Signal Interface Description
Feature/Description
Generate exception for
correctable ECC error
Lockstep Slave
Disallow FPGA
primitives
0 = None
1 = SRL
2 = LUTRAM
3 = Both
Show discrete ports
Processor version
register mode selection
0 = None
1 = Basic
2 = Full
Processor version
register USER1 constant
Processor version
register USER2 constant
Reset value for MSR
register bits IE, BIP, ICE,
DCE, EE, and EIP
Instance Name
Data side AXI interface
Data side LMB interface
Instruction side AXI
interface
Instruction side LMB
interface
Include barrel shifter
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Allowable Default
Values Value Assigned
0,1 0
0, 1 0
0, 1, 2, 3 0
0, 1 0
0, 1, 2 0
0x00-0xff 0x00
0x00000000 0x0000
-0xffffffff 0000
Any 0x0000
combination
of the
individual
bits
Any
micro
instance
blaze
name
0, 1 0
0, 1 1
0, 1 0
0, 1 1
0, 1 0
Send Feedback
Tool
VHDL Type
integer
integer
integer
integer
integer
std_logic_
vector
(0 to 7)
std_logic_
vector
(0 to 31)
std_logic
yes string
integer
integer
integer
integer
integer
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