Xilinx MicroBlaze Reference Manual page 46

Table 2-28: Processor Version Register 4 (PVR4)
Bits Name
0 ICU
1:5 ICTS
6 Reserved
7 ICW
8:10 ICLL
11:15 ICBS
16 IAU
17:18 Reserved
19:21 ICV
22:23 ICS
24 IFTL
25 ICDW
26:31 Reserved
Table 2-29: Processor Version Register 5 (PVR5)
Bits Name
0 DCU
1:5 DCTS
6 Reserved
7 DCW
8:10 DCLL
11:15 DCBS
16 DAU
17 DWB
18 Reserved
19:21 DCV
22:23 Reserved
24 DFTL
25 DCDW
26 AXI4DC
27:31 Reserved
MicroBlaze Processor Reference Guide
UG984 (v2018.2) June 21, 2018
Description
Use instruction cache
Instruction cache tag size
Allow instruction cache write
The base two logarithm of the instruction
cache line length
The base two logarithm of the instruction
cache byte size
The instruction cache is used for all memory
accesses within the cacheable range
Instruction cache victims
Instruction cache streams
Instruction cache tag uses distributed RAM
Instruction cache data width
Description
Use data cache
Data cache tag size
Allow data cache write
The base two logarithm of the data cache line
length
The base two logarithm of the data cache
byte size
The data cache is used for all memory
accesses within the cacheable range
Data cache policy is write-back
Data cache victims
Data cache tag uses distributed RAM
Data cache data width
Data Cache AXI interface uses AXI4 protocol,
with support for exclusive access
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Chapter 2: MicroBlaze Architecture
Value
C_USE_ICACHE
C_ADDR_TAG_BITS
1
C_ALLOW_ICACHE_WR
log2(C_ICACHE_LINE_LEN)
log2(C_CACHE_BYTE_SIZE)
C_ICACHE_ALWAYS_USED
0
0-3: C_ICACHE_VICTIMS = 0,2,4,8
C_ICACHE_STREAMS
C_ICACHE_FORCE_TAG_LUTRAM
C_ICACHE_DATA_WIDTH > 0
0
Value
C_USE_DCACHE
C_DCACHE_ADDR_TAG
1
C_ALLOW_DCACHE_WR
log2(C_DCACHE_LINE_LEN)
log2(C_DCACHE_BYTE_SIZE)
C_DCACHE_ALWAYS_USED
C_DCACHE_USE_WRITEBACK
0
0-3: C_DCACHE_VICTIMS = 0,2,4,8
0
C_DCACHE_FORCE_TAG_LUTRAM
C_DCACHE_DATA_WIDTH > 0
C_M_AXI_DC_EXCLUSIVE_ACCES
S
0
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