Xilinx MicroBlaze Reference Manual page 177

Table 3-19: Configuration Parameters (Cont'd)
Parameter Name
C_DEBUG_TRACE_SIZE
C_DEBUG_PROFILE_SIZE
C_DEBUG_EXTERNAL_TRACE
C_DEBUG_INTERFACE
C_ASYNC_INTERRUPT
C_ASYNC_WAKEUP
C_INTERRUPT_IS_EDGE
C_EDGE_IS_POSITIVE
C_FSL_LINKS
C_USE_EXTENDED_FSL_INSTR
C_ICACHE_BASEADDR
C_ICACHE_HIGHADDR
C_USE_ICACHE
C_ALLOW_ICACHE_WR
C_ICACHE_LINE_LEN
MicroBlaze Processor Reference Guide
UG984 (v2018.2) June 21, 2018
Chapter 3: MicroBlaze Signal Interface Description
Feature/Description
Trace Buffer size
Embedded: 0, ≥ 8192
External: 0, 32 - 8192
Profile Buffer size
External Program Trace
Debug Interface:
0 = Debug Serial
1 = Debug Parallel
2 = AXI4-Lite
Asynchronous Interrupt
Asynchronous Wakeup
Level/Edge Interrupt
Negative/Positive Edge
Interrupt
Number of AXI-Stream
interfaces
Enable use of extended
stream instructions
Instruction cache base
address
Instruction cache high
address
Instruction cache
Instruction cache write
enable
Instruction cache line
length
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Allowable Default Tool
Values Value Assigned
0, 32, 64,
128, 256,
8192,
16384, 8192
32768,
65536,
131072
0, 4096,
8192,
16384,
0
32768,
65536,
131072
0,1 0
0,1,2 0
0,1 0
00,01,10,11 00
0, 1 0
0, 1 1
0-16 0
0, 1 0
0x0 - 0x0
0xFFFFFFFF
FFFFFFFF
0x0 - 0x3FFFF
0xFFFFFFFF FFF
FFFFFFFF
0, 1 0
0, 1 1
4, 8, 16 4
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VHDL Type
integer
integer
yes integer
integer
yes integer
integer
yes
yes integer
integer
yes
integer
integer
std_logic_
vector
std_logic_
vector
integer
integer
integer
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