Xilinx MicroBlaze Reference Manual page 62

• Data Shadow TLB: The DTLB contains data page-translation entries and is fully
associative. The page-translation entries stored in the DTLB represent the most-recently
accessed data-page translations from the UTLB. The DTLB is used to minimize
contention between data translation and UTLB-update operations. The initialization
and management of the DTLB is controlled completely by hardware and is transparent
to software.
The following figure provides the translation flow for TLB.
X-Ref Target - Figure 2-19
Translation Disabled
(MSR[VM]=0)
No Translation
Extract Real
Address from ITLB
Continue I-cache
Access
Route Address
to ITLB
MicroBlaze Processor Reference Guide
UG984 (v2018.2) June 21, 2018
Generate I-side
Effective Address
Translation Enabled
(MSR[VM]=1)
Perform ITLB
Look-Up
ITLB Hit ITLB Miss
Perform UTLB
UTLB Hit
Extract Real
Address from UTLB
Route Address
to DTLB
Figure 2-19: TLB Address Translation Flow
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Chapter 2: MicroBlaze Architecture
Generate D-side
Effective Address
Translation Enabled
(MSR[VM]=1)
Perform DTLB
Look-Up
DTLB Miss DTLB Hit
Look-Up
UTLB Miss
I-Side TLB Miss or
D-Side TLB Miss
Exception
Translation Disabled
(MSR[VM]=0)
No Translation
Extract Real
Address from DTLB
Continue I-cache
or D-cache
Access
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