Xilinx MicroBlaze Reference Manual page 40

The UTLB is not reset by the external reset inputs: Reset and Debug_Rst.
Note:
The following figure illustrates the TLBHI register and
and reset values.
X-Ref Target - Figure 2-15
0
Table 2-21: Translation Look-Aside Buffer High Register (TLBHI)
Bits Name
0:21 TAG
22:24 SIZE
25 V
26 E
27 U0
28:31 Reserved
MicroBlaze Processor Reference Guide
UG984 (v2018.2) June 21, 2018
TAG
Figure 2-15: TLBHI
TLB-entry tag
Is compared with the page number portion of the virtual memory
address under the control of the SIZE field.
Read/Write
Size
Specifies the page size. The SIZE field controls the bit range used in
comparing the TAG field with the page number portion of the virtual
memory address. The page sizes defined by this field are listed in
Table 2-38.
Read/Write
Valid
When this bit is set to 1, the TLB entry is valid and contains a page-
translation entry.
When cleared to 0, the TLB entry is invalid.
Read/Write
Endian
When this bit is set to 1, the page is accessed as a big endian page.
When cleared to 0, the page is accessed as a little endian page.
The E bit only affects data read or data write accesses. Instruction
accesses are not affected.
The E bit is only implemented when the parameter
C_USE_REORDER_INSTR is set to 1, otherwise it is fixed to 0.
Read/Write
User Defined
This bit is fixed to 0, since there are no user defined storage
attributes on MicroBlaze.
Read Only
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Chapter 2: MicroBlaze Architecture
Table 2-21 provides bit descriptions
22
SIZE
Description
25 26 27 28 31
V E U0 Reserved
X19752-091317
Reset Value
0x000000
000
0
0
0
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