Xilinx MicroBlaze Reference Manual page 181

Table 3-19: Configuration Parameters (Cont'd)
Parameter Name
C_M_AXI_DP_PROTOCOL
C_M_AXI_DP_
EXCLUSIVE_ACCESS
C_M_AXI_IP_
THREAD_ID_WIDTH
C_M_AXI_IP_DATA_WIDTH
C_M_AXI_IP_ADDR_WIDTH
C_M_AXI_IP_
SUPPORTS_THREADS
C_M_AXI_IP_SUPPORTS_READ
C_M_AXI_IP_SUPPORTS_WRITE
C_M_AXI_IP_SUPPORTS_
NARROW_BURST
C_M_AXI_IP_PROTOCOL
C_M_AXI_DC_
THREAD_ID_WIDTH
C_M_AXI_DC_DATA_WIDTH
C_M_AXI_DC_ADDR_WIDTH
C_M_AXI_DC_
SUPPORTS_THREADS
C_M_AXI_DC_SUPPORTS_READ
C_M_AXI_DC_SUPPORTS_WRITE
C_M_AXI_DC_SUPPORTS_
NARROW_BURST
C_M_AXI_DC_SUPPORTS_
USER_SIGNALS
MicroBlaze Processor Reference Guide
UG984 (v2018.2) June 21, 2018
Chapter 3: MicroBlaze Signal Interface Description
Feature/Description
Data side AXI protocol
Data side AXI exclusive
access support
Instruction side AXI
thread ID width
Instruction side AXI data
width
Instruction side AXI
address width
Instruction side AXI uses
threads
Instruction side AXI
support for read
accesses
Instruction side AXI
support for write
accesses
Instruction side AXI
narrow burst support
Instruction side AXI
protocol
Data cache AXI ID width
Data cache AXI data
width
Data cache AXI address
width
Data cache AXI uses
threads
Data cache AXI support
for read accesses
Data cache AXI support
for write accesses
Data cache AXI narrow
burst support
Data cache AXI user
signal support
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Allowable Default Tool
Values Value Assigned
AXI4, AXI4
AXI4LITE LITE
0,1 0
1 1
32 32
32-64 32
0 0
1 1
0 0
0 0
AXI4
AXI4LITE
LITE
1 1
32, 64, 128,
32
256, 512
32-64 32
0 0
1 1
1 1
0 0
1 1
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VHDL Type
string
yes
integer
integer
integer
integer
yes
integer
integer
integer
integer
string
integer
integer
integer
yes
integer
integer
integer
integer
integer
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