Xilinx MicroBlaze Reference Manual page 29

Hide thumbs Also See for MicroBlaze:
Table of Contents

Advertisement

Table 2-9: Machine Status Register (MSR) (Cont'd)
Bits
Name
29
C
30
IE
31
-
1. The MMU exceptions (Data Storage Exception, Instruction Storage Exception, Data TLB Miss Exception, Instruction
TLB Miss Exception) cannot be disabled, and are not affected by this bit.
2. This bit is only used for integer divide-by-zero or divide overflow signaling. There is a floating-point equivalent in
the FSR. The DZO-bit flags divide by zero or divide overflow conditions regardless if the processor is configured
with exception handling or not.
Exception Address Register (EAR)
The Exception Address Register stores the full load/store address that caused the exception
for the following:
An unaligned access exception that specifies the unaligned access data address
An
M_AXI_DP
A data storage exception that specifies the (virtual) effective address accessed
An instruction storage exception that specifies the (virtual) effective address read
A data TLB miss exception that specifies the (virtual) effective address accessed
An instruction TLB miss exception that specifies the (virtual) effective address read
The contents of this register is undefined for all other exceptions. When read with the MFS
or MFSE instruction, the EAR is specified by setting Sa = 0x0003. The EAR register is
illustrated in the following figure and
With extended data addressing is enabled (parameter
significant bits of the register are read with the MFS instruction, and the most significant
bits with the MFSE instruction.
X-Ref Target - Figure 2-5
0
MicroBlaze Processor Reference Guide
UG984 (v2018.2) June 21, 2018
Arithmetic Carry
0 = No Carry (Borrow)
1 = Carry (No Borrow)
Read/Write
Interrupt Enable
0 = Interrupts disabled
1 = Interrupts enabled
Read/Write
Reserved
exception that specifies the failing AXI4 data access address
Table 2-10
Figure 2-5: EAR
www.xilinx.com
Chapter 2: MicroBlaze Architecture
Description
provides bit descriptions and reset values.
C_ADDR_SIZE
EAR
Reset Value
0
0
0
> 32), the 32 least
C_ADDR_SIZE - 1
X19742-082517
29
Send Feedback

Advertisement

Table of Contents
loading

Table of Contents