Xilinx MicroBlaze Reference Manual page 28

Table 2-9: Machine Status Register (MSR) (Cont'd)
Bits Name
23 EE
24 DCE
25 DZO
26 ICE
27 FSL
28 BIP
MicroBlaze Processor Reference Guide
UG984 (v2018.2) June 21, 2018
Exception Enable
0 = Hardware exceptions disabled
1 = Hardware exceptions enabled
Only available if configured with exception support
( C_*_EXCEPTION or C_USE_MMU > 0 )
Read/Write
Data Cache Enable
0 = Data Cache disabled
1 = Data Cache enabled
Only available if configured to use data cache (
Read/Write
Division by Zero or Division Overflow
0 = No division by zero or division overflow has occurred
1 = Division by zero or division overflow has occurred
Only available if configured to use hardware divider
( C_USE_DIV = 1 )
Read/Write
Instruction Cache Enable
0 = Instruction Cache disabled
1 = Instruction Cache enabled
Only available if configured to use instruction cache
( C_USE_ICACHE = 1 )
Read/Write
AXI4-Stream Error
0 = get or getd had no error
1 = get or getd control type mismatch
This bit is sticky, that is it is set by a get or getd instruction when a
control bit mismatch occurs. To clear it an MTS or MSRCLR instruction
must be used.
Only available if configured to use stream links (
Read/Write
Break in Progress
0 = No Break in Progress
1 = Break in Progress
Break Sources can be software break instruction or hardware break
from Ext_Brk or Ext_NM_Brk pin.
Read/Write
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Chapter 2: MicroBlaze Architecture
Description
1
C_USE_DCACHE = 1)
2
C_FSL_LINKS > 0 )
Reset Value
0
0
0
0
0
0
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