Data Cache - Xilinx MicroBlaze Reference Manual

Data Cache

Overview
The MicroBlaze processor can be used with an optional data cache for improved
performance. The cached memory range must not include addresses in the LMB address
range. The data cache has the following features:
• Direct mapped (1-way associative)
• Write-through or Write-back
• User selectable cacheable memory address range
• Configurable cache size and tag size
• Caching over AXI4 interface (
• Option to use 4, 8 or 16 word cache-lines
• Cache on and off controlled using a bit in the MSR
• Optional WDC instruction to invalidate or flush data cache lines
• Optional victim cache with write-back to improve performance by saving evicted cache
lines
• Optional parity protection for write-through cache that invalidates cache lines if a Block
RAM bit error is detected
• Optional data width selection to either use 32 bits, an entire cache line, or 512 bits
General Data Cache Functionality
When the data cache is used, the memory address space is split into two segments: a
cacheable segment and a non-cacheable segment. The cacheable area is determined by
two parameters:
range correspond to the cacheable address space. All other addresses are non-cacheable.
The cacheable segment size must be 2
by
C_DCACHE_BASEADDR
range, such that range = 2
zero.
MicroBlaze Processor Reference Guide
UG984 (v2018.2) June 21, 2018
M_AXI_DC
and
C_DCACHE_BASEADDR
N
and
C_DCACHE_HIGHADDR
N
and the N least significant bits of
www.xilinx.com
Chapter 2: MicroBlaze Architecture
)
C_DCACHE_HIGHADDR
, where N is a positive integer. The range specified
must comprise a complete power-of-two
C_DCACHE_BASEADDR
. All addresses within this
must be
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