Xilinx MicroBlaze Reference Manual page 178

Table 3-19: Configuration Parameters (Cont'd)
Parameter Name
C_ICACHE_ALWAYS_USED
C_ICACHE_FORCE_TAG_LUTRAM
C_ICACHE_STREAMS
C_ICACHE_VICTIMS
C_ICACHE_DATA_WIDTH
C_ADDR_TAG_BITS
C_CACHE_BYTE_SIZE
C_DCACHE_BASEADDR
C_DCACHE_HIGHADDR
C_USE_DCACHE
C_ALLOW_DCACHE_WR
C_DCACHE_LINE_LEN
C_DCACHE_ALWAYS_USED
C_DCACHE_FORCE_TAG_LUTRAM
MicroBlaze Processor Reference Guide
UG984 (v2018.2) June 21, 2018
Chapter 3: MicroBlaze Signal Interface Description
Feature/Description
Instruction cache
interface used for all
memory accesses in the
cacheable range
Instruction cache tag
always implemented
with distributed RAM
Instruction cache
streams
Instruction cache
victims
Instruction cache data
width
0 = 32 bits
1 = Full cache line
2 = 512 bits
Instruction cache
address tags
Instruction cache size
Data cache base address
Data cache high address
Data cache
Data cache write enable
Data cache line length
Data cache interface
used for all accesses in
the cacheable range
Data cache tag always
implemented with
distributed RAM
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Allowable Default Tool
Values Value Assigned
0, 1 1
0, 1 0
0, 1 0
0, 2, 4, 8 0
0, 1, 2 0
0-25 17
64, 128,
256, 512,
1024, 2048,
4096, 8192, 8192
16384,
32768,
1
65536
0x0 - 0x0
0xFFFFFFFF
FFFFFFFF
0x0 - 0x3FFFF
0xFFFFFFFF FFF
FFFFFFFF
0, 1 0
0, 1 1
4, 8, 16 4
0, 1 1
0, 1 0
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VHDL Type
integer
integer
integer
integer
integer
yes integer
integer
std_logic_
vector
std_logic_
vector
integer
integer
integer
integer
integer
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