Xilinx MicroBlaze Reference Manual page 47

Table 2-30: Processor Version Register 6 (PVR6)
Bits
0:C_ADDR_SIZE-1
Table 2-31: Processor Version Register 7 (PVR7)
Bits
0:C_ADDR_SIZE-1
Table 2-32: Processor Version Register 8 (PVR8)
Bits
0:C_ADDR_SIZE-1
Table 2-33: Processor Version Register 9 (PVR9)
Bits
0:C_ADDR_SIZE-1
Table 2-34: Processor Version Register 10 (PVR10)
Bits Name
0:7 ARCH
8:13 ASIZE
14:31 Reserved
MicroBlaze Processor Reference Guide
UG984 (v2018.2) June 21, 2018
Name Description
ICBA Instruction Cache Base Address
Name Description
ICHA Instruction Cache High Address
Name Description
DCBA Data Cache Base Address
Name Description
DCHA Data Cache High Address
Description
Target architecture:
0xF = Virtex®-7, Defense Grade Virtex-7 Q
0x10 = Kintex®-7, Defense Grade Kintex-7 Q
0x11 = Artix®-7, Automotive Artix-7,
Defense Grade Artix-7 Q
0x12 = Zynq®-7000, Automotive Zynq-7000,
Defense Grade Zynq-7000 Q
0x13 = UltraScale™ Virtex
0x14 = UltraScale Kintex
0x15 = UltraScale+™ Zynq, Automotive
UltraScale+ Zynq
0x16 = UltraScale+ Virtex
0x17 = UltraScale+ Kintex
0x18 = Spartan®-7, Automotive Spartan-7
Number of extended address bits
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Chapter 2: MicroBlaze Architecture
Value
C_ICACHE_BASEADDR
Value
C_ICACHE_HIGHADDR
Value
C_DCACHE_BASEADDR
Value
C_DCACHE_HIGHADDR
Value
Defined by parameter
C_FAMILY
C_ADDR_SIZE - 32
0
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