Introduction; Overview - Xilinx MicroBlaze Reference Manual

MicroBlaze Architecture

Introduction

This chapter contains an overview of MicroBlaze™ features and detailed information on
MicroBlaze architecture including Big-Endian or Little-Endian bit-reversed format, 32-bit
general purpose registers, virtual-memory management, cache software support, and
AXI4-Stream interfaces.

Overview

The MicroBlaze embedded processor soft core is a reduced instruction set computer (RISC)
optimized for implementation in Xilinx® Field Programmable Gate Arrays (FPGAs). The
following figure shows a functional block diagram of the MicroBlaze core.
X-Ref Target - Figure 2-1
Instruction-side
Bus interface
M_AXI_IC
M_ACE_IC
M_AXI_IP
ILMB
Bus
IF
Optional MicroBlaze feature
MicroBlaze Processor Reference Guide
UG984 (v2018.2) June 21, 2018
Memory Management Unit (MMU)
ITLB UTLB
Program
Counter
Special
Purpose
Registers
Branch Target
Cache
Instruction
Instruction
Buffer Buffer
Instruction
Decode
Figure 2-1: MicroBlaze Core Block Diagram
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Data-side
Bus interface
M_AXI_DC
M_ACE_DC
DTLB
ALU
Shift
M_AXI_DP
Barrel Shift
Bus
IF
Multiplier
Divider
DLMB
FPU
Register File
32 x 32b
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Chapter 2
M0_AXIS ..
M15_AXIS
S0_AXIS ..
S15_AXIS
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