Special Purpose Registers - Xilinx MicroBlaze Reference Manual

Special Purpose Registers

Program Counter (PC)
The program counter (PC) is the 32-bit address of the execution instruction. It can be read
with an MFS instruction, but it cannot be written with an MTS instruction. When used with
the MFS instruction the PC register is specified by setting Sa = 0x0000. The following figure
illustrates the PC and
X-Ref Target - Figure 2-3
0
Table 2-8: Program Counter (PC)
Bits Name
0:31 PC
Machine Status Register (MSR)
The Machine Status Register contains control and status bits for the processor. It can be
read with an MFS instruction. When reading the MSR, bit 29 is replicated in bit 0 as the carry
copy. MSR can be written using either an
instructions.
MSRCLR
When writing to the MSR using
and the remaining bits take effect one clock cycle later. When writing using MTS, all bits
take effect one clock cycle later. Any value written to bit 0 is discarded.
When used with an MTS or MFS instruction, the MSR is specified by setting Sx = 0x0001.
The following table illustrates the MSR register and
and reset values.
X-Ref Target - Figure 2-4
0
CC
MicroBlaze Processor Reference Guide
UG984 (v2018.2) June 21, 2018
Table 2-8 provides a description and reset value.
Figure 2-3: PC
Program Counter
Address of executing instruction, that is, "mfs r2, 0" stores the
address of the mfs instruction itself in R2.
MSRSET
Reserved
Figure 2-4: MSR
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Chapter 2: MicroBlaze Architecture
PC
Description
instruction or the dedicated
MTS
or , the Carry bit takes effect immediately
MSRCLR
Table 2-9
17 18 19 20 21 22 23
VMS VM UMS UM PVR EIP EE
X19740-082517
Reset Value
0x00000000
and
MSRSET
provides the bit description
24 25 26 27 28 29 30
DCE DZO ICE FSL BIP C IE
X19741-091117
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31
31
RES
26