Xilinx MicroBlaze Reference Manual page 302

xori Logical Exclusive OR with Immediate
rD, rA, IMM
xori
1 0 1 0 1 0
0
6
Description
The IMM field is extended to 32 bits by concatenating 16 0-bits on the left. The contents of register
rA are XOR'ed with the extended IMM field; the result is placed into register rD.
Pseudocode
←
(rD) (rA)
Registers Altered
• rD
Latency
• 1 cycle
Notes
By default, Type B Instructions will take the 16-bit IMM field value and sign extend it to 32 bits to use
as the immediate operand. This behavior can be overridden by preceding the Type B instruction with
an imm instruction. See the instruction
When this instruction is used with rD set to r0, a program trace event is emitted with the 14 least
significant bits of the result. Typically this is used to trace operating system events like context
switches and system calls, but it can be used by any program to trace significant events. The
functionality is enabled by setting C_DEBUG_ENABLED = 2 (Extended) and C_DEBUG_TRACE_SIZE > 0.
See "Program and Event Trace" in Chapter 2
MicroBlaze Processor Reference Guide
UG984 (v2018.2) June 21, 2018
rD rA
11
⊕
sext(IMM)
"imm"
www.xilinx.com
Chapter 5: MicroBlaze Instruction Set Architecture
16
for details on using 32-bit immediate values.
for further details.
IMM
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