Data Cache Operation - Xilinx MicroBlaze Reference Manual

The following figure shows the Data Cache organization.
X-Ref Target - Figure 2-23
0
The cacheable data address consists of two parts: the cache address, and the tag address.
The MicroBlaze data cache can be configured from 64 bytes to 64 kB. This corresponds to
a cache address of between 6 and 16 bits. The tag address together with the cache address
should match the full address of cacheable memory. When selecting cache sizes below 2 kB,
distributed RAM is used to implement the Tag RAM and Data RAM, except that block RAM
is always used for the Data RAM when
C_DCACHE_USE_WRITEBACK
RAM, when setting the parameter
only available with cache size 8 kB and less for 4 word cache-lines, with 16 kB and less for
8 word cache-lines, and with 32 kB and less for 16 word cache-lines.
For example, in a MicroBlaze configured with
C_DCACHE_HIGHADDR=0x00403fff
and
C_DCACHE_FORCE_TAG_LUTRAM=0
address, and the 2 kB cache uses 11 bits of byte address, thus the required address tag
width is 14-11=3 bits. The total number of block RAM primitives required in this
configuration is 1 RAMB16 for storing the 512 data words, and 1 RAMB16 for 128 cache line
entries, each consisting of 3 bits of tag, 4 word-valid bits, 1 line-valid bit. In total, 2 RAMB16
primitives.

Data Cache Operation

The caching policy used by the MicroBlaze data cache, write-back or write-through, is
determined by the parameter
write-back protocol is implemented; otherwise write-through is implemented.
However, when configured with an MMU (
(Performance) or 2 (Frequency),
virtual mode is determined by the W storage attribute in the TLB entry, whereas write-back
is used in real mode.
MicroBlaze Processor Reference Guide
UG984 (v2018.2) June 21, 2018
Data Address Bits
Tag Address
Tag
Addr
Tag
RAM
Valid
Load_Instruction
Addr
Data
RAM
Figure 2-23: Data Cache Organization
C_AREA_OPTIMIZED
is not set. Distributed RAM is always used to implement the Tag
C_DCACHE_FORCE_TAG_LUTRAM
,
C_DCACHE_BYTE_SIZE=2048
; the cacheable memory of 16 kB uses 14 bits of byte
C_DCACHE_USE_WRITEBACK
C_USE_MMU
C_DCACHE_USE_WRITEBACK
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Chapter 2: MicroBlaze Architecture
Cache Word Address
=
Cache_Hit
Cache_data
is set to 1 (Area) and
to 1. This parameter is
C_DCACHE_BASEADDR=0x00400000
,
C_DCACHE_LINE_LEN=4
. When this parameter is set, a
> 1,
C_AREA_OPTIMIZED
= 1), the caching policy in
30 31
- -
X19760-091317
,
,
= 0
86
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