Xilinx MicroBlaze Reference Manual page 142

Table 3-1: Summary of MicroBlaze Core I/O (Cont'd)
Signal
IFetch
Instr[0:31]
IReady
IWait
ICE
IUE
Mn_AXIS_TLAST
Mn_AXIS_TDATA
Mn_AXIS_TVALID
Mn_AXIS_TREADY
Sn_AXIS_TLAST
Sn_AXIS_TDATA
Sn_AXIS_TVALID
Sn_AXIS_TREADY
Interrupt
1
Interrupt_Address
1
Interrupt_Ack
Reset
3
Reset_Mode[0:1]
Clk
3
Ext_BRK
3
Ext_NM_BRK
3
MB_Halted
3
Dbg_Stop
MicroBlaze Processor Reference Guide
UG984 (v2018.2) June 21, 2018
Interface I/O
ILMB O Instruction interface LMB instruction fetch
Instruction interface LMB read data bus
ILMB I
ILMB I Instruction interface LMB data ready
ILMB I Instruction interface LMB data wait
Instruction interface LMB correctable error
ILMB I
ILMB I Instruction interface LMB uncorrectable error
M0_AXIS.. O Master interface output AXI4 channels write last
M15_AXIS
Master interface output AXI4 channels write data
M0_AXIS.. O
M15_AXIS
M0_AXIS.. O Master interface output AXI4 channels write valid
M15_AXIS
M0_AXIS.. I Master interface input AXI4 channels write ready
M15_AXIS
Slave interface input AXI4 channels write last
S0_AXIS.. I
S15_AXIS
S0_AXIS.. I Slave interface input AXI4 channels write data
S15_AXIS
S0_AXIS.. I Slave interface input AXI4 channels write valid
S15_AXIS
Slave interface output AXI4 channels write ready
S0_AXIS.. O
S15_AXIS
Core I Interrupt. The signal is synchronized to Clk if the parameter
C_ASYNC_INTERRUPT is set.
Core I Interrupt vector address
Interrupt acknowledge
Core O
Core I Core reset, active high. Should be held for at least 1 Clk clock
cycle.
Core I Reset mode. Sampled when Reset is active.
SeeTable 3-3
2
Core I Clock
Core I Break signal from MDM
Non-maskable break signal from MDM
Core I
Core O Pipeline is halted, either using the Debug Interface, by setting
Dbg_Stop, or by setting Reset_Mode[0:1] to 10.
Core I Unconditionally force pipeline to halt as soon as possible. Rising-
edge detected pulse that should be held for at least 1 Clk clock
cycle. The signal only has any effect when
is greater than 0.
www.xilinx.com
Chapter 3: MicroBlaze Signal Interface Description
Description
for details.
C_DEBUG_ENABL ED
143
Send Feedback