Xilinx MicroBlaze Reference Manual page 301

xor Logical Exclusive OR
rD, rA, rB
xor
1 0 0 0 1 0
0 6
Description
The contents of register rA are XORed with the contents of register rB; the result is placed into register
rD.
Pseudocode
←
(rD) (rA)
Registers Altered
• rD
Latency
• 1 cycle
MicroBlaze Processor Reference Guide
UG984 (v2018.2) June 21, 2018
rD rA
11
⊕
(rB)
www.xilinx.com
Chapter 5: MicroBlaze Instruction Set Architecture
0 0 0 0 0 0 0 0 0 0 0
rB
16 21 31
302
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