Revision History - Xilinx MicroBlaze Reference Manual

Revision History

06/21/2018: Released with Vivado® Design Suite 2018.2 without changes from 2018.1.
The following table shows the revision history for this document.
Date Version
04/04/2018 2018.1
10/04/2017 2017.3
04/05/2017 2017.1
10/05/2016
2016.3
04/06/2016 2016.1
MicroBlaze Processor Reference Guide
UG984 (v2018.2) June 21, 2018
Updated for Vivado 2018.1 release:
• Included information about instruction pipeline hazards and forwarding.
• Clarified that software break does not set the BIP bit in MSR.
• Explained memory scrubbing behavior.
• Added more detailed description of sleep and pause usage.
• Clarified use of parallel debug clock and reset.
Updated for Vivado 2017.3 release:
• Added automotive UltraScale+ Zynq and Spartan-7 devices.
• Updated description of debug trace, to add event trace, new in version 10.0.
• Added 4PB extended address size.
• Clarified description of cache trace signals.
Updated for Vivado 2017.1 release:
• Added description of MMU Physical Address Extension (PAE), new in version 10.0.
• Extended privileged instruction list, and updated instruction descriptions.
• Updated information on debug program trace.
• Added reference to the Triple Modular Redundancy (TMR) subsystem.
• Corrected description of BSIFI instruction.
• Updated MFSE instruction description with PAE information.
• Added MTSE instruction used with PAE, new in version 10.0.
• Updated WDC instruction for external cache invalidate and flush.
Updated for Vivado 2016.3 release:
• Added description of frequency optimized 8-stage pipeline, new in version 10.0.
• Describe bit field instructions, new in version 10.0.
• Include information on parallel debug interface, new in version 10.0.
• Added version 10.0 to MicroBlaze release version code in PVR.
• Included Spartan-7 target architecture in PVR.
• Updated description of MSR reset value.
• Updated Xilinx
Updated for Vivado 2016.1 release:
• Included description of address extension, new in version 9.6.
• Included description of pipeline pause functionality, new in version 9.6
• Included description of non-secure AXI access support, new in version 9.6.
• Included description of hibernate and suspend instructions, new in version 9.6.
• Added version 9.6 to MicroBlaze release version code in PVR.
• Corrected references to
• Replaced references to the deprecated Xilinx Microprocessor Debugger (XMD)
with Xilinx System Debugger (XSDB).
• Removed C code function attributes svc_handler and svc_table_handler.
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Revision
Table 2-46 and Table 2-47.
2
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