Microblaze I/O Overview - Xilinx MicroBlaze Reference Manual

MicroBlaze I/O Overview

The core interfaces shown in the following figure and
• M_AXI_DP: Peripheral Data Interface, AXI4-Lite or AXI4 interface
• DLMB: Data interface, Local Memory Bus (BRAM only)
• M_AXI_IP: Peripheral Instruction interface, AXI4-Lite interface
• ILMB: Instruction interface, Local Memory Bus (BRAM only)
• M0_AXIS..M15_AXIS: AXI4-Stream interface master direct connection interfaces
• S0_AXIS..S15_AXIS: AXI4-Stream interface slave direct connection interfaces
• M_AXI_DC: Data-side cache AXI4 interface
• M_ACE_DC: Data-side cache AXI Coherency Extension (ACE) interface
• M_AXI_IC: Instruction-side cache AXI4 interface
• M_ACE_IC: Instruction-side cache AXI Coherency Extension (ACE) interface
• Core: Miscellaneous signals for: clock, reset, interrupt, debug, trace
X-Ref Target - Figure 3-1
Instruction-side
Bus interface
M_AXI_IC
M_ACE_IC
M_AXI_IP
ILMB
Bus
IF
Optional MicroBlaze feature
MicroBlaze Processor Reference Guide
UG984 (v2018.2) June 21, 2018
Memory Management Unit (MMU)
ITLB UTLB
Program
Counter
Special
Purpose
Registers
Branch Target
Cache
Instruction
Instruction
Buffer Buffer
Instruction
Decode
Figure 3-1: MicroBlaze Core Block Diagram
www.xilinx.com
Chapter 3: MicroBlaze Signal Interface Description
Table 3-1 are defined as follows:
Data-side
Bus interface
DTLB
ALU
Shift
Barrel Shift
Bus
IF
Multiplier
Divider
FPU
Register File
32 x 32b
M_AXI_DC
M_ACE_DC
M_AXI_DP
DLMB
M0_AXIS ..
M15_AXIS
S0_AXIS ..
S15_AXIS
X19738-091117
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