Page 1 MicroBlaze Processor Reference Guide Embedded Development Kit EDK 14.7 UG081 (v14.7)
Page 2: Revision History
(including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of any action brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same.
Page 3 Xilinx EDK 14.1 release 07/25/12 14.2 Xilinx EDK 14.2 release 10/16/12 14.3 Xilinx EDK 14.3 release 12/18/12 14.4 Minor corrections for Xilinx EDK 14.4 release 03/20/13 14.5 EDK 14.5 release 06/19/13 14.6 EDK 14.6 release 10/02/13 14.7 EDK 14.7 release UG081 (v14.7)
Page 4 MicroBlaze Processor Reference Guide www.xilinx.com UG081 (v14.7)
Page 5: Table Of Contents
............92 Chapter 3: MicroBlaze Signal Interface Description Overview .
Page 6 ..........156 Chapter 5: MicroBlaze Instruction Set Architecture Notation .
Page 7: Chapter 1: Introduction
Chapter 1 Introduction The MicroBlaze™ Processor Reference Guide provides information about the 32-bit soft processor, MicroBlaze, which is part of the Embedded Processor Development Kit (EDK). The document is intended as a guide to the MicroBlaze hardware architecture. Guide Contents This guide contains the following chapters: •...
Page 8 Chapter 1: Introduction www.xilinx.com MicroBlaze Processor Reference Guide Send Feedback UG081 (v14.7)
Page 9: Chapter 2: Microblaze Architecture
Fast Simplex Link (FSL) or AXI4-Stream interfaces. Overview The MicroBlaze™ embedded processor soft core is a reduced instruction set computer (RISC) ® optimized for implementation in Xilinx Field Programmable Gate Arrays (FPGAs).
Page 10 Chapter 2: MicroBlaze Architecture Features The MicroBlaze soft core processor is highly configurable, allowing you to select a specific set of features required by your design. The fixed feature set of the processor includes: • Thirty-two 32-bit general purpose registers •...
Page 11 Overview Table 2-1: Configurable Feature Overview by MicroBlaze Version MicroBlaze Versions Feature v7.30 v8.10 v8.20 v8.30 v8.40 v8.50 Hardware exception support option option option option option option Pattern compare instructions option option option option option option Floating point unit (FPU)
Page 12 Chapter 2: MicroBlaze Architecture Table 2-1: Configurable Feature Overview by MicroBlaze Version MicroBlaze Versions Feature v7.30 v8.10 v8.20 v8.30 v8.40 v8.50 Configurable cache data widths option option option option option Count Leading Zeros instruction option option option option option Memory Barrier instruction...
Page 13: Data Types And Endianness
Data Types and Endianness Data Types and Endianness MicroBlaze uses Big-Endian or Little-Endian format to represent data, depending on the parameter C_ENDIANNESS. The hardware supported data types for MicroBlaze are word, half word, and byte. When using the reversed load and store instructions LHUR, LWR, SHR and SWR, the bytes in the data are reversed, as indicated by the byte-reversed order.
Page 14: Instructions
Instructions Instruction Summary All MicroBlaze instructions are 32 bits and are defined as either Type A or Type B. Type A instructions have up to two source register operands and one destination register operand. Type B instructions have one source register and a 16-bit immediate operand (which can be extended to 32 bits by preceding the Type B instruction with an imm instruction).
Page 15 Operation performed on unsigned integer data type float Operation performed on floating point data type clz(r) Count leading zeros Table 2-6: MicroBlaze Instruction Set Summary Type A 6-10 11-15 16-20 21-31 Semantics Type B...
Page 16 Chapter 2: MicroBlaze Architecture Table 2-6: MicroBlaze Instruction Set Summary (Continued) Type A 6-10 11-15 16-20 21-31 Semantics Type B 6-10 11-15 16-31 RSUBKC Rd,Ra,Rb 000111 00000000000 Rd := Rb + Ra + C CMP Rd,Ra,Rb 000101 00000000001 Rd := Rb + Ra + 1 Rd[0] := 0 if (Rb >= Ra) else...
Page 17 Instructions Table 2-6: MicroBlaze Instruction Set Summary (Continued) Type A 6-10 11-15 16-20 21-31 Semantics Type B 6-10 11-15 16-31 TNAPUTD Ra,Rb 010011 00000 0N0TA0 FSL Rb[28:31] := Ra (data write) 00000 MSR[C] := FSL_M_Full if N = 1 TNECAGETD Rd,Rb...
Page 18 Chapter 2: MicroBlaze Architecture Table 2-6: MicroBlaze Instruction Set Summary (Continued) Type A 6-10 11-15 16-20 21-31 Semantics Type B 6-10 11-15 16-31 TNCAPUT Ra,FSLx 011011 00000 1N1TA0000000 & FSLx := Ra (control write, blocking if N = 0) FSLx...
Page 19 Instructions Table 2-6: MicroBlaze Instruction Set Summary (Continued) Type A 6-10 11-15 16-20 21-31 Semantics Type B 6-10 11-15 16-31 WDC.FLUSH Ra,Rb 100100 00000 00001110100 Cache line is flushed, writing stored data to memory, and then cleared. Used when C_DCACHE_USE_WRITEBACK = 1.
Page 20 Chapter 2: MicroBlaze Architecture Table 2-6: MicroBlaze Instruction Set Summary (Continued) Type A 6-10 11-15 16-20 21-31 Semantics Type B 6-10 11-15 16-31 BRLD Rd,Rb 100110 10100 00000000000 PC := PC + Rb Rd := PC BRA Rb 100110 00000 01000...
Page 21 Instructions Table 2-6: MicroBlaze Instruction Set Summary (Continued) Type A 6-10 11-15 16-20 21-31 Semantics Type B 6-10 11-15 16-31 BRI Imm 101110 00000 00000 PC := PC + s(Imm) BRID Imm 101110 00000 10000 PC := PC + s(Imm)
Page 22 Chapter 2: MicroBlaze Architecture Table 2-6: MicroBlaze Instruction Set Summary (Continued) Type A 6-10 11-15 16-20 21-31 Semantics Type B 6-10 11-15 16-31 SB Rd,Ra,Rb 110100 00000000000 Addr := Ra + Rb *Addr[0:8] := Rd[24:31] SBR Rd,Ra,Rb 01000000000 SH Rd,Ra,Rb...
Page 23 For a semaphore operation to work properly, the LWX instruction must be paired with an SWX instruction, and both must specify identical addresses. The reservation granularity in MicroBlaze is a word. For both instructions, the address must be word aligned. No unaligned exceptions are generated for these instructions.
Page 24 Chapter 2: MicroBlaze Architecture Self-modifying Code When using self-modifying code software must ensure that the modified instructions have been written to memory prior to fetching them for execution. There are several aspects to consider: • The instructions to be modified may already have been fetched prior to modification: ♦...
Page 25: Registers
Registers Registers MicroBlaze has an orthogonal instruction set architecture. It has thirty-two 32-bit general purpose registers and up to eighteen 32-bit special purpose registers, depending on configured options. General Purpose Registers The thirty-two 32-bit General Purpose Registers are numbered R0 through R31. The register file is reset on bit stream download (reset value is 0x00000000).
Page 26: Special Purpose Registers
Chapter 2: MicroBlaze Architecture Special Purpose Registers Program Counter (PC) The Program Counter (PC) is the 32-bit address of the execution instruction. It can be read with an MFS instruction, but it cannot be written with an MTS instruction. When used with the MFS instruction the PC register is specified by setting Sa = 0x0000.
Page 27 Read only Exception In Progress 0 = No hardware exception in progress 1 = Hardware exception in progress Only available if configured with exception support (C_*_EXCEPTION or C_USE_MMU > 0) Read/Write MicroBlaze Processor Reference Guide www.xilinx.com Send Feedback UG081 (v14.7)
Page 28 Chapter 2: MicroBlaze Architecture Table 2-9: Machine Status Register (MSR) (Continued) Bits Name Description Reset Value Exception Enable 0 = Hardware exceptions disabled 1 = Hardware exceptions enabled Only available if configured with exception support (C_*_EXCEPTION or C_USE_MMU > 0)
Page 29 2. This bit is only used for integer divide-by-zero or divide overflow signaling. There is a floating point equivalent in the FSR. The DZO-bit flags divide by zero or divide overflow conditions regardless if the processor is configured with exception handling or not. MicroBlaze Processor Reference Guide www.xilinx.com Send Feedback...
Page 30 Chapter 2: MicroBlaze Architecture Exception Address Register (EAR) The Exception Address Register stores the full load/store address that caused the exception for the following: • An unaligned access exception that means the unaligned access address • A DPLB or M_AXI_DP exception that specifies the failing PLB or AXI4 data access address •...
Page 31 00111 = Privileged instruction exception 00111 = Stack protection violation exception 10000 = Data storage exception 10001 = Instruction storage exception 10010 = Data TLB miss exception 10011 = Instruction TLB miss exception Read-only MicroBlaze Processor Reference Guide www.xilinx.com Send Feedback UG081 (v14.7)
Page 32 Chapter 2: MicroBlaze Architecture Table 2-12: Exception Specific Status (ESS) Exception Bits Name Description Reset Value Cause Unaligned Word Access Exception Data Access 0 = unaligned halfword access 1 = unaligned word access Store Access Exception 0 = unaligned load access...
Page 33 TLB miss Branch Target Register (BTR) The Branch Target Register only exists if the MicroBlaze processor is configured to use exceptions. The register stores the branch target address for all delay slot branch instructions executed while MSR[EIP] = 0. If an exception is caused by an instruction in a delay slot (that is, ESR[DS]=1), the exception handler should return execution to the address stored in BTR instead of the normal exception return address stored in R17.
Page 34 Chapter 2: MicroBlaze Architecture Floating Point Status Register (FSR) The Floating Point Status Register contains status bits for the floating point unit. It can be read with an MFS, and written with an MTS instruction. When read or written, the register is specified by setting Sa = 0x0007.
Page 35 The register is only implemented if C_USE_STACK_PROTECTION is set to 1. ↑ Figure 2-11: SHR Table 2-17: Stack High Register (SHR) Bits Name Description Reset Value 0:31 Stack High Register 0xFFFFFFFF MicroBlaze Processor Reference Guide www.xilinx.com Send Feedback UG081 (v14.7)
Page 36 The Process Identifier Register is used to uniquely identify a software process during MMU address translation. It is controlled by the C_USE_MMU configuration option on MicroBlaze. The register is only implemented if C_USE_MMU is greater than 1 (User Mode) and C_AREA_OPTIMIZED is set to 0.
Page 37 The Zone Protection Register is used to override MMU memory protection defined in TLB entries. It is controlled by the C_USE_MMU configuration option on MicroBlaze. The register is only implemented if C_USE_MMU is greater than 1 (User Mode), C_AREA_OPTIMIZED is set to 0, and if the number of specified memory protection zones is greater than zero (C_MMU_ZONES >...
Page 38 Aside Buffer (UTLB) entries. It is controlled by the C_USE_MMU configuration option on MicroBlaze. The register is only implemented if C_USE_MMU is greater than 1 (User Mode), and C_AREA_OPTIMIZED is set to 0. When accessed with the MFS and MTS instructions, the TLBLO is specified by setting Sa = 0x1003.
Page 39 When bit is set to 1, speculative page accesses are not allowed (memory is guarded). When cleared to 0, speculative page accesses are allowed. The G attribute can be used to protect memory-mapped I/O devices from inappropriate instruction accesses. Read/Write MicroBlaze Processor Reference Guide www.xilinx.com Send Feedback UG081 (v14.7)
Page 40 Look-Aside Buffer (UTLB) entries. It is controlled by the C_USE_MMU configuration option on MicroBlaze. The register is only implemented if C_USE_MMU is greater than 1 (User Mode), and C_AREA_OPTIMIZED is set to 0. When accessed with the MFS and MTS instructions, the TLBHI is specified by setting Sa = 0x1004.
Page 41 The E bit is only implemented when the parameter C_USE_REORDER_INSTR is set to 1, otherwise it is fixed to 0. Read/Write User Defined This bit is fixed to 0, since there are no user defined storage attributes on MicroBlaze. Read Only 28:31 Reserved MicroBlaze Processor Reference Guide www.xilinx.com Send Feedback UG081 (v14.7)
Page 42 Look-Aside Buffer (UTLB) when accessing the TLBLO and TLBHI registers. It is controlled by the C_USE_MMU configuration option on MicroBlaze. The register is only implemented if C_USE_MMU is greater than 1 (User Mode), and C_AREA_OPTIMIZED is set to 0. When accessed with the MFS and MTS instructions, the TLBX is specified by setting Sa = 0x1002.
Page 43 Unified Translation Look-Aside Buffer (UTLB). It is controlled by the C_USE_MMU configuration option on MicroBlaze. The register is only implemented if C_USE_MMU is greater than 1 (User Mode), and C_AREA_OPTIMIZED is set to 0. When written with the MTS instruction, the TLBSX is specified by setting Sa = 0x1005.
Page 44 MSR[PVR]=0. • When C_PVR is set to 1 (Basic), MicroBlaze implements only the first register: PVR0, and if set to 2 (Full), all 13 PVR registers (PVR0 to PVR12) are implemented. When read with the MFS instruction the PVR is specified by setting Sa = 0x200x, with x being the register number between 0x0 and 0xB.
Page 45 Use pattern compare and CLZ C_USE_PCMP_INSTR instructions AREA Select implementation to C_AREA_OPTIMIZED optimize area with lower instruction throughput Use barrel shifter C_USE_BARREL Use divider C_USE_DIV Use hardware multiplier C_USE_HW_MUL > 0 (None) MicroBlaze Processor Reference Guide www.xilinx.com Send Feedback UG081 (v14.7)
Page 46 Chapter 2: MicroBlaze Architecture Table 2-26: Processor Version Register 2 (PVR2) (Continued) Bits Name Description Value Use FPU C_USE_FPU > 0 (None) MUL64 Use 64-bit hardware C_USE_HW_MUL = 2 (Mul64) multiplier FPU2 Use floating point conversion C_USE_FPU = 2 (Extended)
Page 47 Description Value Use data cache C_USE_DCACHE DCTS Data cache tag size C_DCACHE_ADDR_TAG Reserved Allow data cache write C_ALLOW_DCACHE_WR 8:10 DCLL The base two logarithm of the log2(C_DCACHE_LINE_LEN) data cache line length MicroBlaze Processor Reference Guide www.xilinx.com Send Feedback UG081 (v14.7)
Page 48 Chapter 2: MicroBlaze Architecture Table 2-29: Processor Version Register 5 (PVR5) (Continued) Bits Name Description Value 11:15 DCBS The base two logarithm of the log2(C_DCACHE_BYTE_SIZE) data cache byte size The data cache is used for all C_DCACHE_ALWAYS_USED memory accesses within the...
Page 49 Number of memory protection zones C_MMU_ZONES PRIVINS Privileged instructions: C_MMU_PRIVILEGED_INSTR 0 = Full protection 1 = Allow stream instructions 16:16 Reserved Reserved for future use 17:31 RSTMSR Reset value for MSR C_RESET_MSR MicroBlaze Processor Reference Guide www.xilinx.com Send Feedback UG081 (v14.7)
Page 50 Chapter 2: MicroBlaze Architecture Table 2-36: Processor Version Register 12 (PVR12) Bits Name Description Value 0:31 VECTORS Location of MicroBlaze vectors C_BASE_VECTORS www.xilinx.com MicroBlaze Processor Reference Guide Send Feedback UG081 (v14.7)
Page 51: Pipeline Architecture
The fetch pipeline stage is then reloaded with a new instruction from the calculated branch address. A taken branch in MicroBlaze takes three clock cycles to execute, two of which are required for refilling the pipeline. To reduce this latency overhead, MicroBlaze supports branches with delay slots.
Page 52 Chapter 2: MicroBlaze Architecture Delay Slots When executing a taken branch with delay slot, only the fetch pipeline stage in MicroBlaze is flushed. The instruction in the decode stage (branch delay slot) is allowed to complete. This technique effectively reduces the branch penalty from two clock cycles to one. Branch instructions with delay slots have a D appended to the instruction mnemonic.
Page 53: Memory Architecture
(more if the posted-write buffer in the memory controller is full). The MicroBlaze instruction and data caches can be configured to use 4 or 8 word cache lines. When using a longer cache line, more bytes are prefetched, which generally improves performance for software with sequential access patterns.
Page 54: Privileged Instructions
Chapter 2: MicroBlaze Architecture Privileged Instructions The following MicroBlaze instructions are privileged: • GET, GETD,PUT,PUTD (except when explicitly allowed) • WIC, WDC • • MSRCLR, MSRSET (except when only the C bit is affected) • • RTID, RTBD, RTED •...
Page 55: Virtual-Memory Management
Virtual-Memory Management Virtual-Memory Management Programs running on MicroBlaze use effective addresses to access a flat 4 GB address space. The processor can interpret this address space in one of two ways, depending on the translation mode: • In real mode, effective addresses are used to directly access physical memory •...
Page 56: Virtual Mode
Chapter 2: MicroBlaze Architecture straightforward than a virtual-mode memory manager. Real mode is often an appropriate solution for memory management in simple embedded environments, when access-protection is necessary, but virtual address translation is not required. Virtual Mode In virtual mode, the processor translates an effective address into a physical address using the...
Page 57 TLB. Translation Look-Aside Buffer The translation look-aside buffer (TLB) is used by the MicroBlaze MMU for address translation when the processor is running in virtual mode, memory protection, and storage control. Each entry within the TLB contains the information necessary to identify a virtual page (PID and effective page number), specify its translation into a physical page, determine the protection characteristics of the page, and specify the storage attributes associated with the page.
Page 58 Chapter 2: MicroBlaze Architecture The MicroBlaze TLB is physically implemented as three separate TLBs: • Unified TLB—The UTLB contains 64 entries and is pseudo-associative. Instruction-page and data-page translation can be stored in any UTLB entry. The initialization and management of the UTLB is controlled completely by software.
Page 59 256 KB TAG[0:13] - Address[0:13] Address[14:31] RPN[0:13] 14:21 1 MB TAG[0:11] - Address[0:11] Address[12:31] RPN[0:11] 12:21 4 MB TAG[0:9] - Address[0:9] Address[10:31] RPN[0:9] 10:21 16 MB TAG[0:7] - Address[0:7] Address[8:31] RPN[0:7] 8:21 MicroBlaze Processor Reference Guide www.xilinx.com Send Feedback UG081 (v14.7)
Page 60 Chapter 2: MicroBlaze Architecture TLB Access When the MMU translates a virtual address (the combination of PID and effective address) into a physical address, it first examines the appropriate shadow TLB for the page translation entry. If an entry is found, it is used to access physical memory. If an entry is not found, the MMU examines the UTLB for the entry.
Page 61 Virtual-Memory Management system software initializes the UTLB with page-translation entries, management of the MicroBlaze UTLB is usually performed using interrupt handlers running in real mode. Figure 2-21 diagrams the general process for examining a TLB entry. TLBHI[V]=1 TLB-Entry Miss TLBHI[TID]=0x00...
Page 62 Chapter 2: MicroBlaze Architecture • From privileged mode: The TLB entry specifies a read-only page (TLBLO[WR]=0) that is not otherwise ♦ overridden by the zone field (ZPR[Zn]‚ 10 and ZPR[Zn]‚ 11). This applies to store instructions. Instruction-Storage Exception When virtual mode is enabled, (MSR[VM]=1), an instruction-storage exception occurs when access to a page is not permitted for any of the following reasons: •...
Page 63 MFS or MTS instructions to completely access an entry. The UTLB is searched for a specific translation using the TLBSX register. TLBSX locates a translation using an effective address and loads the corresponding UTLB index into the TLBX register. MicroBlaze Processor Reference Guide www.xilinx.com Send Feedback...
Page 64 Solving the above problems in an efficient manner requires keeping track of page accesses and page modifications. MicroBlaze does not track page access and page modification in hardware. Instead, system software can use the TLB-miss exceptions and the data-storage exception to collect this information.
Page 65: Reset, Interrupts, Exceptions, And Break
0x00000000, but the parameter C_BASE_VECTORS can be used to locate them anywhere in memory. The address range 0x28 to 0x4F is reserved for future software support by Xilinx. Allocating these addresses for user applications is likely to conflict with future releases of EDK support software.
Page 66 Instruction Storage Exception, Data TLB Miss Exception, and Instruction TLB Miss Exception. A hardware exception causes MicroBlaze to flush the pipeline and branch to the hardware exception vector (address C_BASE_VECTORS + 0x20). The execution stage instruction in the exception cycle is not executed.
Page 67 ♦ The data Processor Local Bus exception is caused by an active error signal from the slave (DPLB_MRdErr or DPLB_MWrErr) or timeout signal from the arbiter (DPLB_MTimeout). MicroBlaze Processor Reference Guide www.xilinx.com Send Feedback UG081 (v14.7)
Page 68 Chapter 2: MicroBlaze Architecture The data side local memory (DLMB) can only cause instruction bus exception when ♦ C_FAULT_TOLERANT is set to 1, and either an uncorrectable error occurs in the LMB memory, as indicated by the DUE signal, or C_ECC_USE_CE_EXCEPTION is set to 1 and a correctable error occurs in the LMB memory, as indicated by the DCE signal.
Page 69 R16. MicroBlaze also sets the Break In Progress (BIP) flag in the Machine Status Register (MSR). A normal hardware break (that is, the Ext_BRK input port) is only handled when MSR[BIP] and MSR[EIP] are set to 0 (that is, there is no break or exception in progress).
Page 70 Xilinx Microprocesor Debugger (XMD) tool, irrespective of the value of C_BASE_VECTORS. Latency The time it takes MicroBlaze to enter a break service routine from the time the break occurs depends on the instruction currently in the execution stage and the latency to the memory storing the break vector.
Page 71 Latency The time it takes MicroBlaze to enter an Interrupt Service Routine (ISR) from the time an interrupt occurs, depends on the configuration of the processor and the latency of the memory controller storing the interrupt vectors. If MicroBlaze is configured to have a hardware divider, the largest latency happens when an interrupt occurs during the execution of a division instruction.
Page 72: Instruction Cache
The cacheable instruction address consists of two parts: the cache address, and the tag address. The MicroBlaze instruction cache can be configured from 64 bytes to 64 kB. This corresponds to a cache address of between 6 and 16 bits. The tag address together with the cache address should match the full address of cacheable memory.
Page 73: Instruction Cache
With the AXI4 interface, C_ICACHE_DATA_WIDTH determines the amount of data transferred from the stream buffer each clock cycle, either 32 bits or an entire cache line. To be able to use instruction cache stream buffers, area optimization must not be enabled. MicroBlaze Processor Reference Guide www.xilinx.com Send Feedback...
Page 74: Data Cache
Data Cache Overview MicroBlaze can be used with an optional data cache for improved performance. The cached memory range must not include addresses in the LMB address range. The data cache has the following features: •...
Page 75: Data Cache
The cacheable data address consists of two parts: the cache address, and the tag address. The MicroBlaze data cache can be configured from 64 bytes to 64 kB. This corresponds to a cache address of between 6 and 16 bits. The tag address together with the cache address should match the full address of cacheable memory.
Page 76: Data Cache Operation
Chapter 2: MicroBlaze Architecture Data Cache Operation The caching policy used by the MicroBlaze data cache, write-back or write-through, is determined by the parameter C_DCACHE_USE_WRITEBACK. When this parameter is set, a write-back protocol is implemented, otherwise write-through is implemented. However, when configured with an MMU (C_USE_MMU >...
Page 77 M_AXI_DP or PLB. This can be done by writing to a semaphore immediately before turning off caches, and then in a loop poll until it has been written. MicroBlaze Processor Reference Guide www.xilinx.com Send Feedback...
Page 78 Chapter 2: MicroBlaze Architecture The contents of the cache are preserved when the cache is disabled. WDC Instruction The optional WDC instruction (C_ALLOW_DCACHE_WR=1) is used to invalidate or flush cache lines in the data cache from an application. For a detailed description, please refer to...
Page 79: Floating Point Unit (Fpu)
Figure 2-24: IEEE 754 Single Precision Format The value of a floating point number v in MicroBlaze has the following interpretation: If exponent = 255 and fraction <> 0, then v= NaN, regardless of the sign bit sign * ∞...
Page 80 If the two nearest representable values are equally near, then the one with its least significant bit zero is returned. Operations All MicroBlaze FPU operations use the processors general purpose registers rather than a dedicated floating point register file, see “General Purpose Registers”.
Page 81 The EDK compiler system, based on GCC, provides support for the Floating Point Unit compliant with the MicroBlaze API. Compiler flags are automatically added to the GCC command line based on the type of FPU present in the system, when using XPS or SDK.
Page 82 Chapter 2: MicroBlaze Architecture float sum, t; int i; sum = 0.0f; for (i = 1; i <= 10; i++) { t = (float)i; sum += t * t; The above code requires a cast from an integer to a float on each loop iteration. This can be rewritten float sum, t;...
Page 83: Stream Link Interfaces
The interfaces on MicroBlaze are 32 bits wide. A separate bit indicates whether the sent/received word is of control or data type. The get instruction in the MicroBlaze ISA is used to transfer information from a port to a general purpose register. The put instruction is used to transfer data in the opposite direction.
Page 84: Debug And Trace
When the DBG_STOP input is set to 1, MicroBlaze will halt after a few instructions. XMD will detect that MicroBlaze has halted, and indicate where the halt occured. The signal can be used to halt MicroBlaze at any external event, for example when a ChipScope™ logic analyzer is triggered.
Page 85: Fault Tolerance
It is possible to manually override fault tolerance support in MicroBlaze, by explicitly disabling C_FAULT_TOLERANT in the MicroBlaze configuration dialog. This is not recommended, unless no block RAM is used in MicroBlaze, and there is no need to handle bus exceptions from uncorrectable ECC errors.
Page 86 With fault tolerance enabled, if an error occurs in LMB block RAM, the LMB BRAM Interface Controller generates error signals on the LMB interface. If exceptions are enabled in MicroBlaze, by setting the EE bit in the Machine Status Register, the uncorrectable error signal either generates an instruction bus exception or a data bus exception, depending on the affected interface.
Page 87 LMB block RAM and all MicroBlaze internal block RAMs used in a particular configuration. This function is intended to be called periodically from a timer interrupt routine. The following example code illustrates how this can be done.
Page 88 The standalone BSP BRAM driver is used to access the ECC registers in the LMB BRAM Interface Controller, and also provides a comprehensive self test. By implementing the SDK Xilinx C Project "Peripheral Tests", a self-test example including the BRAM self test for each LMB BRAM Interface Controller in the system is generated. Depending on the ECC features enabled in the LMB BRAM Interface Controller, this code will perform all possible tests of the ECC function.
Page 89 The system is suitable when area constraints are high, and there is no need for testing of the ECC function, or analysis of error frequency and location. No ECC registers are implemented. Single bit errors are corrected by the ECC logic before being passed to MicroBlaze. Uncorrectable errors set an error signal, which generates an exception in MicroBlaze.
Page 90 Correctable Error First Failing Address Register and set the CE_STATUS bit in the ECC Status Register. An interrupt will be generated triggering MicroBlaze to read the failing address and then perform a read followed by a write on the failing address. This will remove the single bit error from the BRAM, thus reducing the risk of the single bit error becoming a uncorrectable double bit error.
Page 91: Lockstep Operation
The outputs from the master MicroBlaze core drive the peripherals in the system. All data leaving the protected area pass through inhibitors. Each inhibitor is controlled from its associated comparator.
Page 92: Error Detection
In this system two redundant MicroBlaze processors run in lockstep. A comparator is used to signal an error when a mis-match is detected on the outputs of the two processors. Any error immediately causes both processors to halt, preventing further error propagation.
Page 93 Master ILMB BRAM Controller Lockstep_Out MicroBlaze Debug I/O Interfaces Debug Module Comparator External Memory Interfaces Debug Lockstep_Out MicroBlaze Inputs Slave Inputs Inputs C_LOCKSTEP_SLAVE = 1 Figure 2-27: Lockstep Error Detection Application MicroBlaze Processor Reference Guide www.xilinx.com Send Feedback UG081 (v14.7)
Page 94 Chapter 2: MicroBlaze Architecture www.xilinx.com MicroBlaze Processor Reference Guide Send Feedback UG081 (v14.7)
Page 95: Chapter 3: Microblaze Signal Interface Description
This chapter describes the types of signal interfaces that can be used to connect MicroBlaze™. Overview The MicroBlaze core is organized as a Harvard architecture with separate bus interface units for data and instruction accesses. The following four memory interfaces are supported: Local Memory Bus ®...
Page 96: Microblaze I/O Overview
DWFSL 0..15: FSL master direct connection interfaces SFSL 0..15: FSL slave interfaces DRFSL 0..15: FSL slave direct connection interfaces DXCL: Data side Xilinx CacheLink interface (FSL master/slave pair) M_AXI_DC: Data side cache AXI4 interface M_ACE_DC: Data side cache ACE interface...
Page 97 MicroBlaze I/O Overview Table 3-1: Summary of MicroBlaze Core I/O Signal Interface Description M_AXI_DP_AWID Master Write address ID M_AXI_DP M_AXI_DP_AWADDR M_AXI_DP Master Write address M_AXI_DP_AWLEN M_AXI_DP Master Burst length M_AXI_DP_AWSIZE M_AXI_DP Master Burst size M_AXI_DP_AWBURST M_AXI_DP Master Burst type M_AXI_DP_AWLOCK...
Page 98 Chapter 3: MicroBlaze Signal Interface Description Table 3-1: Summary of MicroBlaze Core I/O (Continued) Signal Interface Description M_AXI_DP_RID M_AXI_DP Slave Read ID tag M_AXI_DP_RDATA M_AXI_DP Slave Read data M_AXI_DP_RRESP M_AXI_DP Slave Read response M_AXI_DP_RLAST Slave Read last M_AXI_DP M_AXI_DP_RVALID M_AXI_DP...
Page 99 MicroBlaze I/O Overview Table 3-1: Summary of MicroBlaze Core I/O (Continued) Signal Interface Description M_AXI_IP_ARCACHE M_AXI_IP Master Cache type M_AXI_IP_ARPROT M_AXI_IP Master Protection type M_AXI_IP_ARQOS M_AXI_IP Master Quality of Service M_AXI_IP_ARVALID Master Read address valid M_AXI_IP M_AXI_IP_ARREADY M_AXI_IP Slave Read address ready...
Page 100 Chapter 3: MicroBlaze Signal Interface Description Table 3-1: Summary of MicroBlaze Core I/O (Continued) Signal Interface Description M_AXI_DC_BID M_AXI_DC Slave Response ID M_AXI_DC_BVALID M_AXI_DC Slave Write response valid M_AXI_DC_BREADY M_AXI_DC Master Response ready M_AXI_DC_BUSER Slave Write response user signals M_AXI_DC...
Page 101 MicroBlaze I/O Overview Table 3-1: Summary of MicroBlaze Core I/O (Continued) Signal Interface Description M_AXI_DC_ACREADY M_ACE_DC Master Snoop ready M_AXI_DC_CRREADY M_ACE_DC Slave Snoop response ready M_AXI_DC_CRVALID M_ACE_DC Master Snoop response valid M_AXI_DC_CRRESP Master Snoop response M_ACE_DC M_AXI_DC_CDVALID M_ACE_DC Master Snoop data valid...
Page 102 Chapter 3: MicroBlaze Signal Interface Description Table 3-1: Summary of MicroBlaze Core I/O (Continued) Signal Interface Description M_AXI_IC_BREADY M_AXI_IC Master Response ready M_AXI_IC_BUSER M_AXI_IC Slave Write response user signals M_AXI_IC_WACK M_ACE_IC Slave Write acknowledge M_AXI_IC_ARID Master Read address ID M_AXI_IC...
Page 103 MicroBlaze I/O Overview Table 3-1: Summary of MicroBlaze Core I/O (Continued) Signal Interface Description M_AXI_IC_CRVALID M_ACE_IC Master Snoop response valid M_AXI_IC_CRRESP M_ACE_IC Master Snoop response M_AXI_IC_CDVALID M_ACE_IC Master Snoop data valid Slave Snoop data ready M_AXI_IC_CDREADY M_ACE_IC Master Snoop data...
Page 104 Chapter 3: MicroBlaze Signal Interface Description Table 3-1: Summary of MicroBlaze Core I/O (Continued) Signal Interface Description DPLB Data Interface PLB address acknowledge DPLB_MAddrAck DPLB Data Interface PLB terminate read burst DPLB_MRdBTerm indicator DPLB Data Interface PLB read data acknowledge...
Page 105 MicroBlaze I/O Overview Table 3-1: Summary of MicroBlaze Core I/O (Continued) Signal Interface Description IPLB Instruction Interface PLB slave write error IPLB_MWrErr indicator IPLB Instruction Interface PLB slave interrupt IPLB_MIRQ indicator IPLB Instruction Interface PLB terminate write IPLB_MWrBTerm burst indicator...
Page 106 Chapter 3: MicroBlaze Signal Interface Description Table 3-1: Summary of MicroBlaze Core I/O (Continued) Signal Interface Description ILMB Instruction interface LMB data ready IReady ILMB Instruction interface LMB data wait IWait ILMB Instruction interface LMB correctable error ILMB Instruction interface LMB uncorrectable error M0_AXIS..
Page 107 2. The Reset and MB_Reset signals are functionally equivalent. MB_Reset is intended for the AXI4 and PLB interfaces. 3. MicroBlaze is a synchronous design clocked with the Clk signal, except for hardware debug logic, which is clocked with the Dbg_Clk signal. If hardware debug logic is not used, there is no minimum frequency limit for Clk.
Page 108: Axi4 And Ace Interface Description
This interface can have multiple outstanding transactions, either issuing up to 2 transactions when reading, or up to 32 transactions when writing. MicroBlaze ensures that all outstanding writes are completed before a read is issued, since the processor must maintain an ordered memory model but AXI or ACE has separate read/write channels without any ordering.
Page 109 AXI4 and ACE Interface Description Interface Parameters and Signals The relationship between MicroBlaze parameter settings and AXI4 interface behavior for tool- assigned parameters is summarized in Table 3-2. Table 3-2: AXI Memory Mapped Interface Parameters Interface Parameter Description AXI4-Lite: Default.
Page 110 Chapter 3: MicroBlaze Signal Interface Description Values for access permissions, memory types, quality of service and shareability domain are defined Table 3-3. Table 3-3: AXI Interface Signal Definitions Interface Signal Description Access Permission: M_AXI_IP C_M_AXI_IP_ARPROT • Unprivileged, secure instruction access (100)
Page 111: Processor Local Bus (Plb) Interface Description
FSLn_M_Control and FSLn_S_Control signals, respectively. Write Operation A write to the stream interface is performed by MicroBlaze using one of the put or putd instructions. A write operation transfers the register contents to an output AXI4 interface. The transfer is completed in a single clock cycle for blocking mode writes (put and cput instructions) as long as the interface is not busy.
Page 112: Local Memory Bus (Lmb) Interface Description
Correctable error Uncorrectable error Bus clock 1. Added in LMB for MicroBlaze v8.00 Addr[0:31] The address bus is an output from the core and indicates the memory address that is being accessed by the current transfer. It is valid only when AS is high. In multicycle accesses (accesses requiring more than one clock cycle to complete), Addr[0:31] is valid only in the first clock cycle of the transfer.
Page 113 It is sampled on the rising edge of the clock. For reads, this signal indicates the Data_Read[0:31] bus is valid, and for writes it indicates that the Data_Write[0:31] bus has been written to local memory. MicroBlaze Processor Reference Guide www.xilinx.com Send Feedback...
Page 114 Data_Read[0:31] bus is erroneous, and for byte and halfword writes it indicates that the corresponding data word in local memory was erroneous before writing the new data. All operations on the LMB are synchronous to the MicroBlaze core clock. LMB Transactions The following diagrams provide examples of LMB bus operations.
Page 115 Figure 3-3: LMB Generic Write Operation, N Wait States Generic Read Operations Addr Byte_Enable Data_Write Read_Strobe Write_Strobe Data_Read Ready Wait Don’t Care Figure 3-4: LMB Generic Read Operation, 0 Wait States MicroBlaze Processor Reference Guide www.xilinx.com Send Feedback UG081 (v14.7)
Page 116 Chapter 3: MicroBlaze Signal Interface Description Addr Byte_Enable Data_Write Read_Strobe Write_Strobe Data_Read Ready Wait Don’t Care Figure 3-5: LMB Generic Read Operation, N Wait States Back-to-Back Write Operation Addr Byte_Enable Data_Write Read_Strobe Write_Strobe Data_Read Ready Wait Don’t Care Don’t Care Don’t Care...
Page 117 Don’t Care Figure 3-7: LMB Back-to-Back Read Operation Back-to-Back Mixed Write/Read Operation Addr Byte_Enable Data_Write Read_Strobe Write_Strobe Data_Read Ready Wait Don’t Care Figure 3-8: Back-to-Back Mixed Write/Read Operation, 0 Wait States MicroBlaze Processor Reference Guide www.xilinx.com Send Feedback UG081 (v14.7)
Page 118 Chapter 3: MicroBlaze Signal Interface Description Addr Byte_Enable Data_Write Read_Strobe Write_Strobe Data_Read Ready Wait Don’t Care Don’t Care Don’t Care Figure 3-9: Back-to-Back Mixed Write/Read Operation, N Wait States www.xilinx.com MicroBlaze Processor Reference Guide Send Feedback UG081 (v14.7)
Page 119 • byte transfers to byte devices MicroBlaze does not support transfers that are larger than the addressed device. These types of transfers require dynamic bus sizing and conversion cycles that are not supported by the MicroBlaze bus interface. Data steering for read cycles are shown in...
Page 120 Other masters may have more restrictive requirements for byte lane placement than those allowed by MicroBlaze. Slave devices are typically attached “left-justified” with byte devices attached to the most-significant byte lane, and halfword devices attached to the most significant halfword lane.
Page 121: Fast Simplex Link (Fsl) Interface Description
Full Bit indicating output FSL input FSLn_M_Full std_logic FIFO is full when set Slave FSL Signal Interface MicroBlaze may contain up to 16 slave FSL interfaces. The slave FSL interface signals are depicted Table 3-11. Table 3-11: Slave FSL Signals Signal Name...
Page 122 FSL BUS Write Operation A write to the FSL bus is performed by MicroBlaze using one of the put or putd instructions. A write operation transfers the register contents to an output FSL bus. The transfer is completed in a single clock cycle for blocking mode writes to the FSL (put and cput instructions) as long as the FSL FIFO does not become full.
Page 123: Xilinx Cachelink (Xcl) Interface Description
Figure 3-10: CacheLink Connection with Integrated FSL Buffers (Only Instruction Cache Used in this Example) The interface is only available on MicroBlaze when caches are enabled. It is legal to use a CacheLink cache on the instruction side or the data side without caching the other.
Page 124 Chapter 3: MicroBlaze Signal Interface Description Table 3-12: MicroBlaze Cache Link Signals (Continued) Signal Name Description VHDL Type Direction Read data from I-side return std_logic_ input ICACHE_FSL_IN_Data read data FSL vector (0 to 31) FSL control-bit from I-side std_logic input ICACHE_FSL_IN_Control return read data FSL.
Page 125 Xilinx CacheLink (XCL) Interface Description Table 3-12: MicroBlaze Cache Link Signals (Continued) Signal Name Description VHDL Type Direction FSL control-bit to D-side read std_logic output DCACHE_FSL_OUT_Control access FSL. Used with address bits [30 to 31] for read/write, byte enable and burst write encoding.
Page 126: Data Cache Read Miss
Chapter 3: MicroBlaze Signal Interface Description • Linear fetch is used by the IXCL2 and DXCL2 protocol, selected when C_ICACHE_INTERFACE = 1 (IXCL2) and C_DCACHE_INTERFACE = 1 (DXCL2), respectively. The address output on the CacheLink is then aligned to the cache line size (that is, if an access to address 0x348 is a miss with a 4 word cache line, then the address output on the CacheLink is 0x340).
Page 127 Xilinx CacheLink (XCL) Interface Description With the DXCL2 protocol (linear fetch): Store words from DCACHE_FSL_IN_Data to the cache Forward the requested word to the execution unit in order to resume execution Store remaining words from DCACHE_FSL_IN_Data to the cache Data Cache Write When C_DCACHE_INTERFACE is set to 1 (DXCL2), the CacheLink can either do burst write or single-word write.
Page 128: Lockstep Interface Description
Chapter 3: MicroBlaze Signal Interface Description Lockstep Interface Description The lockstep interface on MicroBlaze is designed to connect a master and one or more slave MicroBlaze instances. The lockstep signals on MicroBlaze are listed in Table 3-13. Table 3-13: MicroBlaze Lockstep Signals...
Page 129 Lockstep Interface Description Table 3-14: MicroBlaze Lockstep Comparison Signals (Continued) Signal Name Bus Index Range VHDL Type 198 to 201 std_logic_vector IPLB_M_size 202 to 217 std_logic_vector IPLB_M_TAttribute 218 to 220 std_logic_vector IPLB_M_type 221 to 348 std_logic_vector IPLB_M_wrDBus std_logic DPLB_M_ABort std_logic...
Page 130 Chapter 3: MicroBlaze Signal Interface Description Table 3-14: MicroBlaze Lockstep Comparison Signals (Continued) Signal Name Bus Index Range VHDL Type 712 to 715 std_logic_vector M_AXI_IP_AWCACHE 716 to 718 std_logic_vector M_AXI_IP_AWPROT 719 to 722 std_logic_vector M_AXI_IP_AWQOS std_logic M_AXI_IP_AWVALID 724 to 755...
Page 131 Lockstep Interface Description Table 3-14: MicroBlaze Lockstep Comparison Signals (Continued) Signal Name Bus Index Range VHDL Type 962 to 964 std_logic_vector M_AXI_DP_ARSIZE 965 to 966 std_logic_vector M_AXI_DP_ARBURST std_logic M_AXI_DP_ARLOCK 968 to 971 std_logic_vector M_AXI_DP_ARCACHE 972 to 974 std_logic_vector M_AXI_DP_ARPROT 975 to 978...
Page 132 Chapter 3: MicroBlaze Signal Interface Description Table 3-14: MicroBlaze Lockstep Comparison Signals (Continued) Signal Name Bus Index Range VHDL Type 2784 std_logic M_AXI_IC_WACK 2785 std_logic_vector M_AXI_IC_ARID 2786 to 2907 std_logic_vector M_AXI_IC_ARADDR 2818 to 2825 std_logic_vector M_AXI_IC_ARLEN 2826 to 2828 std_logic_vector...
Page 133 Lockstep Interface Description Table 3-14: MicroBlaze Lockstep Comparison Signals (Continued) Signal Name Bus Index Range VHDL Type 3515 std_logic M_AXI_DC_WLAST 3516 std_logic M_AXI_DC_WVALID 3517 std_logic M_AXI_DC_WUSER 3518 std_logic M_AXI_DC_BREADY 3519 std_logic M_AXI_DC_WACK 3520 std_logic M_AXI_DC_ARID 3521 to 3552 std_logic_vector M_AXI_DC_ARADDR...
Page 134 Chapter 3: MicroBlaze Signal Interface Description Table 3-14: MicroBlaze Lockstep Comparison Signals (Continued) Signal Name Bus Index Range VHDL Type 3737 to 3768 std_logic_vector Trace_Data_Address 3769 to 3800 std_logic_vector Trace_Data_Write_Value 3801 to 3804 std_logic_vector Trace_Data_Byte_Enable 3805 std_logic Trace_Data_Access 3806 std_logic...
Page 135: Debug Interface Description
Module (MDM) IP core. The MDM is controlled by the Xilinx Microprocessor Debugger (XMD) through the JTAG port of the FPGA. The MDM can control multiple MicroBlaze processors at the same time. The debug signals are grouped in the DEBUG bus. The debug signals on MicroBlaze are listed in Table 3-15.
Page 136 Trace_MB_Halted 1. Valid only when Trace_Valid_Instr = 1 2. Updated for MicroBlaze v7.00: 4 bits added to Trace_MSR_Reg, Trace_PID_Reg added, Trace_MB_Halted added, and 1 bit added to Trace_Exception Kind 3. Valid only when Trace_Exception_Taken = 1 4. Updated for MicroBlaze v7.30: Trace_DCache_Rdy, Trace_DCache_Read, Trace_ICache_Rdy, and Trace_Jump_Hit added 5.
Page 137 External non maskable break 01100 External maskable break 10000 Data storage exception 10001 Instruction storage exception 10010 Data TLB miss exception 10011 Instruction TLB miss exception 1. Added for MicroBlaze v7.00 MicroBlaze Processor Reference Guide www.xilinx.com Send Feedback UG081 (v14.7)
Page 138: Microblaze Core Configurability
Chapter 3: MicroBlaze Signal Interface Description MicroBlaze Core Configurability The MicroBlaze core has been developed to support a high degree of user configurability. This allows tailoring of the processor to meet specific cost/performance requirements. Configuration is done via parameters that typically enable, size, or select certain processor features.
Page 139 Include barrel shifter 0, 1 integer C_USE_BARREL Include hardware divider 0, 1 integer C_USE_DIV Include hardware integer C_USE_HW_MUL multiplier 0 = None 0, 1, 2 1 = Mul32 2 = Mul64 MicroBlaze Processor Reference Guide www.xilinx.com Send Feedback UG081 (v14.7)
Page 140 Chapter 3: MicroBlaze Signal Interface Description Table 3-18: MPD Parameters (Continued) Allowable Default Tool Parameter Name Feature/Description VHDL Type Values Value Assig Include hardware floating integer C_USE_FPU point unit 0 = None 0, 1, 2 1 = Basic 2 = Extended...
Page 141 Instruction cache high 0x00000000 - 0x3FFF std_logic_vector C_ICACHE_HIGHADDR address 0xFFFFFFFF FFFF Instruction cache 0, 1 integer C_USE_ICACHE Instruction cache write integer C_ALLOW_ICACHE_WR 0, 1 enable Instruction cache line integer C_ICACHE_LINE_LEN 4, 8 length MicroBlaze Processor Reference Guide www.xilinx.com Send Feedback UG081 (v14.7)
Page 142 Chapter 3: MicroBlaze Signal Interface Description Table 3-18: MPD Parameters (Continued) Allowable Default Tool Parameter Name Feature/Description VHDL Type Values Value Assig Instruction cache interface integer C_ICACHE_ALWAYS_USED used for all memory 0, 1 accesses in the cacheable range Instruction cache...
Page 143 Data side PLB data width integer C_DPLB_DWIDTH Data side PLB native data integer C_DPLB_NATIVE_DWIDTH width Data side PLB burst enable integer C_DPLB_BURST_EN Data side PLB Point-to- integer C_DPLB_P2P 0, 1 point MicroBlaze Processor Reference Guide www.xilinx.com Send Feedback UG081 (v14.7)
Page 144 Chapter 3: MicroBlaze Signal Interface Description Table 3-18: MPD Parameters (Continued) Allowable Default Tool Parameter Name Feature/Description VHDL Type Values Value Assig Instruction side PLB data integer C_IPLB_DWIDTH width Instruction side PLB integer C_IPLB_NATIVE_DWIDTH native data width Instruction side PLB burst...
Page 145 C_M_AXI_DP_PROTOCOL AXI4LITE LITE Data side AXI exclusive integer C_M_AXI_DP_ access support EXCLUSIVE_ACCESS Data side AXI read integer C_INTERCONNECT_ accesses issued M_AXI_DP_READ_ISSUING Data side AXI write integer C_INTERCONNECT_ accesses issued M_AXI_DP_WRITE_ISSUING MicroBlaze Processor Reference Guide www.xilinx.com Send Feedback UG081 (v14.7)
Page 146 Chapter 3: MicroBlaze Signal Interface Description Table 3-18: MPD Parameters (Continued) Allowable Default Tool Parameter Name Feature/Description VHDL Type Values Value Assig Instruction side AXI integer C_M_AXI_IP_ thread ID width THREAD_ID_WIDTH Instruction side AXI data integer C_M_AXI_IP_DATA_WIDTH width Instruction side AXI...
Page 147 Instruction cache AXI integer C_M_AXI_IC_SUPPORTS_WRITE support for write accesses Instruction cache AXI integer C_M_AXI_IC_SUPPORTS_ narrow burst support NARROW_BURST Instruction cache AXI user integer C_M_AXI_IC_SUPPORTS_ signal support USER_SIGNALS MicroBlaze Processor Reference Guide www.xilinx.com Send Feedback UG081 (v14.7)
Page 148 Chapter 3: MicroBlaze Signal Interface Description Table 3-18: MPD Parameters (Continued) Allowable Default Tool Parameter Name Feature/Description VHDL Type Values Value Assig Instruction cache AXI string C_M_AXI_IC_PROTOCOL AXI4 AXI4 protocol Instruction cache AXI user integer C_M_AXI_IC_AWUSER_WIDTH width Instruction cache AXI user...
Page 149 Spartan aspartan3 aspartan3a aspartan3adsp aspartan3e aspartan6 qspartan6 qspartan6l spartan3 spartan3a spartan3adsp spartan3an spartan3e spartan6 spartan6l Virtex qrvirtex4 qrvirtex5 qvirtex4 qvirtex5 qvirtex6 qvirtex7 virtex4 virtex5 virtex6 virtex6l virtex7 Zynq azynq zynq qzynq MicroBlaze Processor Reference Guide www.xilinx.com Send Feedback UG081 (v14.7)
Page 150 Chapter 3: MicroBlaze Signal Interface Description www.xilinx.com MicroBlaze Processor Reference Guide Send Feedback UG081 (v14.7)
Page 151: Chapter 4: Microblaze Application Binary Interface
MicroBlaze Application Binary Interface This chapter describes MicroBlaze™ Application Binary Interface (ABI), which is important for developing software in assembly language for the soft processor. The MicroBlaze GNU compiler follows the conventions described in this document. Any code written by assembly programmers should also follow the same conventions to be compatible with the compiler generated code.
Page 152: Register Usage Conventions
Chapter 4: MicroBlaze Application Binary Interface Register Usage Conventions The register usage convention for MicroBlaze is given in Table 4-2. Table 4-2: Register Usage Conventions Register Type Enforcement Purpose Dedicated Value 0 Dedicated Stack Pointer Dedicated Read-only small data area anchor...
Page 153: Stack Convention
Stack Convention The architecture for MicroBlaze defines 32 general purpose registers (GPRs). These registers are classified as volatile, non-volatile, and dedicated. • The volatile registers (also known as caller-save) are used as temporaries and do not retain values across the function calls. Registers R3 through R12 are volatile, of which R3 and R4 are used for returning values to the caller function, if any.
Page 154 Chapter 4: MicroBlaze Application Binary Interface Table 4-3: Stack Convention High Address Function Parameters for called sub-routine (Arg n .. Arg1) (Optional: Maximum number of arguments required for any called procedure from the current procedure). Old Stack Pointer Link Register (R15) Callee Saved Register (R31..R19)
Page 155: Memory Model
Global initialized variables which are small in size are stored in this area. The threshold for deciding the size of the variable to be stored in the small data area is set to 8 bytes in the MicroBlaze C compiler (mb-gcc), but this can be changed by giving a command line option to the compiler.
Page 156: Interrupt And Exception Handling
__attribute__((fast_interrupt)); MicroBlaze allows exception and interrupt handler routines to be located at any address location addressable using 32 bits. The user exception handler code starts with the label _exception_handler, the hardware exception handler starts with _hw_exception_handler, while the interrupt handler code starts with the label _interrupt_handler for interrupts that do not use low-latency handlers.
Page 157 Interrupt and Exception Handling In the current MicroBlaze system, there are dummy routines for interrupt and user exception handling, which you can change. In order to override these routines and link your own interrupt and exception handlers, you must define the handler code with specific attributes.
Page 158 Chapter 4: MicroBlaze Application Binary Interface www.xilinx.com MicroBlaze Processor Reference Guide Send Feedback UG081 (v14.7)
Page 159: Chapter 5: Microblaze Instruction Set Architecture
Chapter 5 MicroBlaze Instruction Set Architecture This chapter provides a detailed guide to the Instruction Set Architecture of MicroBlaze™. Notation The symbols used throughout this chapter are defined in Table 5-1. Table 5-1: Symbol Notation Symbol Meaning Subtract × Multiply Divide ∧...
Page 160 Chapter 5: MicroBlaze Instruction Set Architecture Table 5-1: Symbol Notation (Continued) Symbol Meaning sext(x) Sign-extend x Mem(x) Memory location at address x FSLx Stream interface x (FSL or AXI) LSW(x) Least Significant Word of x isDnz(x) Floating point: true if x is denormalized isInfinite(x) Floating point: true if x is +∞...
Page 161: Formats
Source Reg A Immediate Value Instructions This section provides descriptions of MicroBlaze instructions. Instructions are listed in alphabetical order. For each instruction Xilinx provides the mnemonic, encoding, a description, pseudocode of its semantics, and a list of registers that it modifies.
Page 162 Chapter 5: MicroBlaze Instruction Set Architecture Arithmetic Add rD, rA, rB addc rD, rA, rB Add with Carry addk rD, rA, rB Add and Keep Carry addkc rD, rA, rB Add with Carry and Keep Carry 0 0 0 K C 0...
Page 163 This behavior can be overridden by preceding the Type B instruction with an imm instruction. See the instruction “imm,” page 204 for details on using 32-bit immediate values. MicroBlaze Processor Reference Guide www.xilinx.com Send Feedback UG081 (v14.7)
Page 164 Chapter 5: MicroBlaze Instruction Set Architecture Logical AND rD, rA, rB 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 Description The contents of register rA are ANDed with the contents of register rB; the result is placed into register rD.
Page 165 This behavior can be overridden by preceding the Type B instruction with an imm instruction. See the instruction “imm,” page 204 for details on using 32-bit immediate values. MicroBlaze Processor Reference Guide www.xilinx.com Send Feedback UG081 (v14.7)
Page 166 Chapter 5: MicroBlaze Instruction Set Architecture andn Logical AND NOT andn rD, rA, rB 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 Description The contents of register rA are ANDed with the logical complement of the contents of register rB;...
Page 167 This behavior can be overridden by preceding the Type B instruction with an imm instruction. See the instruction “imm,” page 204 for details on using 32-bit immediate values. MicroBlaze Processor Reference Guide www.xilinx.com Send Feedback UG081 (v14.7)
Page 168 Chapter 5: MicroBlaze Instruction Set Architecture Branch if Equal rA, rB Branch if Equal beqd rA, rB Branch if Equal with Delay 1 0 0 1 1 1 D 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Description Branch if rA is equal to 0, to the instruction located in the offset value of rB.
Page 169 A delay slot must not be used by the following: imm, branch, or break instructions. Interrupts and external hardware breaks are deferred until after the delay slot branch has been completed. MicroBlaze Processor Reference Guide www.xilinx.com Send Feedback UG081 (v14.7)
Page 170 Chapter 5: MicroBlaze Instruction Set Architecture Branch if Greater or Equal rA, rB Branch if Greater or Equal bged rA, rB Branch if Greater or Equal with Delay 1 0 0 1 1 1 D 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 Description Branch if rA is greater or equal to 0, to the instruction located in the offset value of rB.
Page 171 A delay slot must not be used by the following: imm, branch, or break instructions. Interrupts and external hardware breaks are deferred until after the delay slot branch has been completed. MicroBlaze Processor Reference Guide www.xilinx.com Send Feedback UG081 (v14.7)
Page 172 Chapter 5: MicroBlaze Instruction Set Architecture Branch if Greater Than rA, rB Branch if Greater Than bgtd rA, rB Branch if Greater Than with Delay 1 0 0 1 1 1 D 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 Description Branch if rA is greater than 0, to the instruction located in the offset value of rB.
Page 173 A delay slot must not be used by the following: imm, branch, or break instructions. Interrupts and external hardware breaks are deferred until after the delay slot branch has been completed. MicroBlaze Processor Reference Guide www.xilinx.com Send Feedback UG081 (v14.7)
Page 174 Chapter 5: MicroBlaze Instruction Set Architecture Branch if Less or Equal rA, rB Branch if Less or Equal bled rA, rB Branch if Less or Equal with Delay 1 0 0 1 1 1 D 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 Description Branch if rA is less or equal to 0, to the instruction located in the offset value of rB.
Page 175 A delay slot must not be used by the following: imm, branch, or break instructions. Interrupts and external hardware breaks are deferred until after the delay slot branch has been completed. MicroBlaze Processor Reference Guide www.xilinx.com Send Feedback UG081 (v14.7)
Page 176 Chapter 5: MicroBlaze Instruction Set Architecture Branch if Less Than rA, rB Branch if Less Than bltd rA, rB Branch if Less Than with Delay 1 0 0 1 1 1 D 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 Description Branch if rA is less than 0, to the instruction located in the offset value of rB.
Page 177 A delay slot must not be used by the following: imm, branch, or break instructions. Interrupts and external hardware breaks are deferred until after the delay slot branch has been completed. MicroBlaze Processor Reference Guide www.xilinx.com Send Feedback UG081 (v14.7)
Page 178 Chapter 5: MicroBlaze Instruction Set Architecture Branch if Not Equal rA, rB Branch if Not Equal bned rA, rB Branch if Not Equal with Delay 1 0 0 1 1 1 D 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 Description Branch if rA not equal to 0, to the instruction located in the offset value of rB.
Page 179 A delay slot must not be used by the following: imm, branch, or break instructions. Interrupts and external hardware breaks are deferred until after the delay slot branch has been completed. MicroBlaze Processor Reference Guide www.xilinx.com Send Feedback UG081 (v14.7)
Page 180 Chapter 5: MicroBlaze Instruction Set Architecture Unconditional Branch Branch Branch Absolute Branch with Delay brad Branch Absolute with Delay brld rD, rB Branch and Link with Delay brald rD, rB Branch Absolute and Link with Delay 1 0 0 1 1 0...
Page 181 The instructions brl and bral are not available. A delay slot must not be used by the following: imm, branch, or break instructions. Interrupts and external hardware breaks are deferred until after the delay slot branch has been completed. MicroBlaze Processor Reference Guide www.xilinx.com Send Feedback...
Page 182 If the D bit is not set, it means that there is no delay slot, so the instruction to be executed after the branch is the target instruction. As a special case, when MicroBlaze is configured to use an MMU (C_USE_MMU >= 1) and “bralid rD, C_BASE_VECTORS+0x8“ is used to perform a User Vector Exception, the Machine Status Register bits User Mode and Virtual Mode are cleared.
Page 183 A delay slot must not be used by the following: imm, branch, or break instructions. Interrupts and external hardware breaks are deferred until after the delay slot branch has been completed. MicroBlaze Processor Reference Guide www.xilinx.com Send Feedback UG081 (v14.7)
Page 184 The BIP flag in the MSR will be set, and the reservation bit will be cleared. When MicroBlaze is configured to use an MMU (C_USE_MMU >= 1) this instruction is privileged. This means that if the instruction is attempted in User Mode (MSR[UM] = 1) a Privileged Instruction exception occurs.
Page 185 User Mode (MSR[UM] = 1) a Privileged Instruction exception occurs. As a special case, when MicroBlaze is configured to use an MMU (C_USE_MMU >= 1) and “brki rD, C_BASE_VECTORS+0x8” or “brki rD, C_BASE_VECTORS+0x18” is used to perform a Software Break, the Machine Status Register bits User Mode and Virtual Mode are cleared.
Page 186 • Latency • 1 cycle with C_AREA_OPTIMIZED=0 • 2 cycles with C_AREA_OPTIMIZED=1 Note These instructions are optional. To use them, MicroBlaze has to be configured to use barrel shift instructions (C_USE_BARREL=1). www.xilinx.com MicroBlaze Processor Reference Guide Send Feedback UG081 (v14.7)
Page 187 2 cycles with C_AREA_OPTIMIZED=1 Notes These are not Type B Instructions. There is no effect from a preceding imm instruction. These instructions are optional. To use them, MicroBlaze has to be configured to use barrel shift instructions (C_USE_BARREL=1). MicroBlaze Processor Reference Guide www.xilinx.com...
Page 188 Chapter 5: MicroBlaze Instruction Set Architecture Count Leading Zeros rD, rA Count leading zeros in rA 1 0 0 1 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 Description This instruction counts the number of leading zeros in register rA starting from the most significant bit.
Page 189 If the U bit is clear, rA and rB is considered signed values. Pseudocode ← (rA) + 1 (rD) (rB) + ← (rD)(MSB) (rA) > (rB) Registers Altered • Latency • 1 cycle MicroBlaze Processor Reference Guide www.xilinx.com Send Feedback UG081 (v14.7)
Page 190 ESR[EC], if an FP exception is generated • FSR[IO,UF,OF,DO] Latency • 4 cycles with C_AREA_OPTIMIZED=0 • 6 cycles with C_AREA_OPTIMIZED=1 Note This instruction is only available when the MicroBlaze parameter C_USE_FPU is greater than 0. www.xilinx.com MicroBlaze Processor Reference Guide Send Feedback UG081 (v14.7)
Page 191 ESR[EC], if an FP exception is generated • FSR[IO,UF,OF,DO] Latency • 4 cycles with C_AREA_OPTIMIZED=0 • 6 cycles with C_AREA_OPTIMIZED=1 Note This instruction is only available when the MicroBlaze parameter C_USE_FPU is greater than 0. MicroBlaze Processor Reference Guide www.xilinx.com Send Feedback UG081 (v14.7)
Page 192 ESR[EC], if an FP exception is generated • FSR[IO,UF,OF,DO] Latency • 4 cycles with C_AREA_OPTIMIZED=0 • 6 cycles with C_AREA_OPTIMIZED=1 Note This instruction is only available when the MicroBlaze parameter C_USE_FPU is greater than 0. www.xilinx.com MicroBlaze Processor Reference Guide Send Feedback UG081 (v14.7)
Page 193 ESR[EC], if an FP exception is generated • FSR[IO,UF,OF,DO,DZ] Latency • 28 cycles with C_AREA_OPTIMIZED=0, 30 cycles with C_AREA_OPTIMIZED=1 Note This instruction is only available when the MicroBlaze parameter C_USE_FPU is greater than 0. MicroBlaze Processor Reference Guide www.xilinx.com Send Feedback UG081 (v14.7)
Page 194 • 1 cycle with C_AREA_OPTIMIZED=0 • 3 cycles with C_AREA_OPTIMIZED=1 Note These instructions are only available when the MicroBlaze parameter C_USE_FPU is greater than Table 5-2, page 195 lists the floating point comparison operations. www.xilinx.com MicroBlaze Processor Reference Guide Send Feedback...
Page 195 ← 00110 ESR[EC] ← 1 ← 0 ← 1 ← 0 ← 0 Greater-or-equal (rD) (rD) (rD) (rD) (rD) ← 1 ← 1 FSR[IO] FSR[IO] ← 00110 ← 00110 ESR[EC] ESR[EC] MicroBlaze Processor Reference Guide www.xilinx.com Send Feedback UG081 (v14.7)
Page 196 ((rA)) Registers Altered • Latency • 4 cycles with C_AREA_OPTIMIZED=0 • 6 cycles with C_AREA_OPTIMIZED=1 Note This instruction is only available when the MicroBlaze parameter C_USE_FPU is set to 2 (Extended). www.xilinx.com MicroBlaze Processor Reference Guide Send Feedback UG081 (v14.7)
Page 197 ESR[EC], if an FP exception is generated • FSR[IO,DO] Latency • 5 cycles with C_AREA_OPTIMIZED=0 • 7 cycles with C_AREA_OPTIMIZED=1 Note This instruction is only available when the MicroBlaze parameter C_USE_FPU is set to 2 (Extended). MicroBlaze Processor Reference Guide www.xilinx.com Send Feedback UG081 (v14.7)
Page 198 ESR[EC], if an FP exception is generated • FSR[IO,DO] Latency • 27 cycles with C_AREA_OPTIMIZED=0 • 29 cycles with C_AREA_OPTIMIZED=1 Note This instruction is only available when the MicroBlaze parameter C_USE_FPU is set to 2 (Extended). www.xilinx.com MicroBlaze Processor Reference Guide Send Feedback UG081 (v14.7)
Page 199 FSLx Description MicroBlaze will read from the link x interface and place the result in register rD. If the available number of links set by C_FSL_LINKS is less than or equal to FSLx, link 0 is used. The get instruction has 32 variants.
Page 200 • 2 cycles with C_AREA_OPTIMIZED=1 The blocking versions of this instruction will stall the pipeline of MicroBlaze until the instruction can be completed. Interrupts are served when the parameter C_USE_EXTENDED_FSL_INSTR is set to 1, and the instruction is not atomic.
Page 201 0 0 0 0 0 Description MicroBlaze will read from the interface defined by the four least significant bits in rB and place the result in register rD. If the available number of links set by C_FSL_LINKS is less than or equal to the four least significant bits in rB, link 0 is used.
Page 202 1 cycle with C_AREA_OPTIMIZED=0 • 2 cycles with C_AREA_OPTIMIZED=1 The blocking versions of this instruction will stall the pipeline of MicroBlaze until the instruction can be completed. Interrupts are served unless the instruction is atomic, which ensures that the instruction cannot be interrupted.
Page 203 1 cycle if (rA) = 0, otherwise 32 cycles with C_AREA_OPTIMIZED=0 • 1 cycle if (rA) = 0, otherwise 34 cycles with C_AREA_OPTIMIZED=1 Note This instruction is only valid if MicroBlaze is configured to use a hardware divider (C_USE_DIV = MicroBlaze Processor Reference Guide www.xilinx.com Send Feedback...
Page 204 16-bit immediate value field, a 32-bit immediate value cannot be used directly. However, 32- bit immediate values can be used in MicroBlaze. By default, Type B Instructions will take the 16-bit IMM field value and sign extend it to 32 bits to use as the immediate operand. This behavior can be overridden by preceding the Type B instruction with an imm instruction.
Page 205 ESR[DIZ], if a data storage exception is generated Latency • 1 cycle with C_AREA_OPTIMIZED=0 • 2 cycles with C_AREA_OPTIMIZED=1 Note The byte reversed instruction is only valid if MicroBlaze is configured to use reorder instructions (C_USE_REORDER_INSTR = 1). MicroBlaze Processor Reference Guide www.xilinx.com Send Feedback UG081 (v14.7)
Page 206 Chapter 5: MicroBlaze Instruction Set Architecture lbui Load Byte Unsigned Immediate lbui rD, rA, IMM 1 1 1 0 0 0 Description Loads a byte (8 bits) from the memory location that results from adding the contents of register rA with the value in IMM, sign-extended to 32 bits.
Page 207 ESR[W], ESR[Rx], if an unaligned data access exception is generated Latency • 1 cycle with C_AREA_OPTIMIZED=0 • 2 cycles with C_AREA_OPTIMIZED=1 Note The halfword reversed instruction is only valid if MicroBlaze is configured to use reorder instructions (C_USE_REORDER_INSTR = 1). MicroBlaze Processor Reference Guide www.xilinx.com Send Feedback UG081 (v14.7)
Page 208 Chapter 5: MicroBlaze Instruction Set Architecture lhui Load Halfword Unsigned Immediate lhui rD, rA, IMM 1 1 1 0 0 1 Description Loads a halfword (16 bits) from the halfword aligned memory location that results from adding the contents of register rA and the value in IMM, sign-extended to 32 bits. The data is placed in the least significant halfword of register rD and the most significant halfword in rD is cleared.
Page 209 ESR[W], ESR[Rx], if an unaligned data access exception is generated Latency • 1 cycle with C_AREA_OPTIMIZED=0 • 2 cycles with C_AREA_OPTIMIZED=1 Note The word reversed instruction is only valid if MicroBlaze is configured to use reorder instructions (C_USE_REORDER_INSTR = 1). MicroBlaze Processor Reference Guide www.xilinx.com Send Feedback UG081 (v14.7)
Page 210 Chapter 5: MicroBlaze Instruction Set Architecture Load Word Immediate rD, rA, IMM 1 1 1 0 1 0 Description Loads a word (32 bits) from the word aligned memory location that results from adding the contents of register rA and the value IMM, sign-extended to 32 bits. The data is placed in register rD. A data TLB miss exception occurs if virtual protected mode is enabled, and a valid translation entry corresponding to the address is not found in the TLB.A data storage exception occurs if access is...
Page 211 ESR[EC] 00100;ESR[ECC] ← ← ← ← MSR[UMS] MSR[UM]; MSR[VMS] MSR[VM]; MSR[UM] 0; MSR[VM] else ← ← (rD) Mem(Addr); Reservation ≠ if AXI_Exclusive(Addr) and AXI_Response EXOKAY then ← MSR[C] else ← MSR[C] MicroBlaze Processor Reference Guide www.xilinx.com Send Feedback UG081 (v14.7)
Page 212 Chapter 5: MicroBlaze Instruction Set Architecture Registers Altered • rD and MSR[C], unless an exception is generated, in which case they are unchanged • MSR[UM], MSR[VM], MSR[UMS], MSR[VMS], if a TLB miss exception or a data storage exception is generated •...
Page 213 User Mode (MSR[UM] = 1) a Privileged Instruction exception occurs. When the most significant bit in IMM is set to 1 and no exception occurs, MicroBlaze enters sleep mode after all outstanding accesses have been completed, and sets the Sleep output signal to indicate this.
Page 214 Chapter 5: MicroBlaze Instruction Set Architecture Move From Special Purpose Register rD, rS 1 0 0 1 0 1 0 0 0 0 0 1 0 Description Copies the contents of the special purpose register rS into register rD. The special purpose registers TLBLO and TLBHI are used to copy the contents of the Unified TLB entry indexed by TLBX.
Page 215 (dependent on pipeline stall behavior). An instruction that does not affect FSR must precede the MFS instruction to guarantee correct FSR value. EAR, ESR and BTR are only valid as operands when at least one of the MicroBlaze C_*_EXCEPTION parameters are set to 1.
Page 216 Bit positions in the IMM value that are 1 are cleared in the MSR. Bit positions that are 0 in the IMM value are left untouched. When MicroBlaze is configured to use an MMU (C_USE_MMU >= 1) this instruction is privileged for all IMM values except those only affecting C. This means that if the instruction is attempted in User Mode (MSR[UM] = 1) in this case a Privileged Instruction exception occurs.
Page 217 1 are set in the MSR. Bit positions that are 0 in the IMM value are left untouched. When MicroBlaze is configured to use an MMU (C_USE_MMU >= 1) this instruction is privileged for all IMM values except those only affecting C. This means that if the instruction is attempted in User Mode (MSR[UM] = 1) in this case a Privileged Instruction exception occurs.
Page 218 Chapter 5: MicroBlaze Instruction Set Architecture When setting MSR[VM] the instruction must always be followed by a synchronizing branch instruction, for example BRI 4. www.xilinx.com MicroBlaze Processor Reference Guide Send Feedback UG081 (v14.7)
Page 219 TLBLO and TLBHI are used to copy to the Unified TLB entry indexed by TLBX. When MicroBlaze is configured to use an MMU (C_USE_MMU >= 1) this instruction is privileged. This means that if the instruction is attempted in User Mode (MSR[UM] = 1) a Privileged Instruction exception occurs.
Page 220 The PC, ESR, EAR, BTR, EDR and PVR0 - PVR12 cannot be written by the MTS instruction. The FSR is only valid as a destination if the MicroBlaze parameter C_USE_FPU is greater than 0. The SLR and SHR are only valid as a destination if the MicroBlaze parameter C_USE_STACK_PROTECTION is set to 1.
Page 221 1 cycle with C_AREA_OPTIMIZED=0 • 3 cycles with C_AREA_OPTIMIZED=1 Note This instruction is only valid if the target architecture has multiplier primitives, and if present, the MicroBlaze parameter C_USE_HW_MUL is greater than 0. MicroBlaze Processor Reference Guide www.xilinx.com Send Feedback UG081 (v14.7)
Page 222 MicroBlaze parameter C_USE_HW_MUL is set to 2 (Mul64). When MULH is used, bit 30 and 31 in the MUL instruction must be zero to distinguish between the two instructions. In previous versions of MicroBlaze, these bits were defined as zero, but the actual values were not relevant.
Page 223 MicroBlaze parameter C_USE_HW_MUL is set to 2 (Mul64). When MULHU is used, bit 30 and 31 in the MUL instruction must be zero to distinguish between the two instructions. In previous versions of MicroBlaze, these bits were defined as zero, but the actual values were not relevant.
Page 224 MicroBlaze parameter C_USE_HW_MUL is set to 2 (Mul64). When MULHSU is used, bit 30 and 31 in the MUL instruction must be zero to distinguish between the two instructions. In previous versions of MicroBlaze, these bits were defined as zero, but the actual values were not relevant.
Page 225 “imm,” page 204 for details on using 32-bit immediate values. This instruction is only valid if the target architecture has multiplier primitives, and if present, the MicroBlaze parameter C_USE_HW_MUL is greater than 0. MicroBlaze Processor Reference Guide www.xilinx.com Send Feedback...
Page 226 Chapter 5: MicroBlaze Instruction Set Architecture Logical OR rD, rA, rB 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Description The contents of register rA are ORed with the contents of register rB; the result is placed into register rD.
Page 227 This behavior can be overridden by preceding the Type B instruction with an imm instruction. See the instruction “imm,” page 204 for details on using 32-bit immediate values. MicroBlaze Processor Reference Guide www.xilinx.com Send Feedback UG081 (v14.7)
Page 228 Chapter 5: MicroBlaze Instruction Set Architecture pcmpbf Pattern Compare Byte Find pcmpbf rD, rA, rB bytewise comparison returning position of first match 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 Description The contents of register rA is bytewise compared with the contents in register rB.
Page 229 (rB) = (rA) then ← (rD) else ← (rD) Registers Altered • Latency • 1 cycle Note This instruction is only available when the parameter C_USE_PCMP_INSTR is set to 1. MicroBlaze Processor Reference Guide www.xilinx.com Send Feedback UG081 (v14.7)
Page 230 Chapter 5: MicroBlaze Instruction Set Architecture pcmpne Pattern Compare Not Equal pcmpne rD, rA, rB equality comparison with a negative boolean result 1 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 Description The contents of register rA is compared with the contents in register rB.
Page 231 FSLx Description MicroBlaze will write the value from register rA to the link x interface. If the available number of links set by C_FSL_LINKS is less than or equal to FSLx, link 0 is used. The put instruction has 16 variants.
Page 232 • 2 cycles with C_AREA_OPTIMIZED=1 The blocking versions of this instruction will stall the pipeline of MicroBlaze until the instruction can be completed. Interrupts are served when the parameter C_USE_EXTENDED_FSL_INSTR is set to 1, and the instruction is not atomic.
Page 233 0 0 0 0 0 0 Description MicroBlaze will write the value from register rA to the link interface defined by the four least significant bits in rB. If the available number of links set by C_FSL_LINKS is less than or equal to the four least significant bits in rB, link 0 is used.
Page 234 1 cycle with C_AREA_OPTIMIZED=0 • 2 cycles with C_AREA_OPTIMIZED=1 The blocking versions of this instruction will stall the pipeline of MicroBlaze until the instruction can be completed. Interrupts are served unless the instruction is atomic, which ensures that the instruction cannot be interrupted.
Page 235 In subtractions, Carry = (Borrow). When the Carry is set by a subtraction, it means that there is no Borrow, and when the Carry is cleared, it means that there is a Borrow. MicroBlaze Processor Reference Guide www.xilinx.com Send Feedback...
Page 236 Chapter 5: MicroBlaze Instruction Set Architecture rsubi Arithmetic Reverse Subtract Immediate rsubi rD, rA, IMM Subtract Immediate rsubic rD, rA, IMM Subtract Immediate with Carry rsubik rD, rA, IMM Subtract Immediate and Keep Carry rsubikc rD, rA, IMM Subtract Immediate with Carry and Keep Carry...
Page 237 That delay slot instruction has breaks disabled. When MicroBlaze is configured to use an MMU (C_USE_MMU >= 1) this instruction is privileged. This means that if the instruction is attempted in User Mode (MSR[UM] = 1) a Privileged Instruction exception occurs.
Page 238 That delay slot instruction has interrupts disabled. When MicroBlaze is configured to use an MMU (C_USE_MMU >= 1) this instruction is privileged. This means that if the instruction is attempted in User Mode (MSR[UM] = 1) a Privileged Instruction exception occurs.
Page 239 This instruction always has a delay slot. The instruction following the RTED is always executed before the branch target. When MicroBlaze is configured to use an MMU (C_USE_MMU >= 1) this instruction is privileged. This means that if the instruction is attempted in User Mode (MSR[UM] = 1) a Privileged Instruction exception occurs.
Page 240 Chapter 5: MicroBlaze Instruction Set Architecture rtsd Return from Subroutine rtsd rA, IMM 1 0 1 1 0 1 1 0 0 0 0 Description Return from subroutine will branch to the location specified by the contents of rA plus the IMM field, sign-extended to 32 bits.
Page 241 ESR[DIZ], if a data storage exception is generated Latency • 1 cycle with C_AREA_OPTIMIZED=0 • 2 cycles with C_AREA_OPTIMIZED=1 Note The byte reversed instruction is only valid if MicroBlaze is configured to use reorder instructions (C_USE_REORDER_INSTR = 1). MicroBlaze Processor Reference Guide www.xilinx.com Send Feedback UG081 (v14.7)
Page 242 Chapter 5: MicroBlaze Instruction Set Architecture Store Byte Immediate rD, rA, IMM 1 1 1 1 0 0 Description Stores the contents of the least significant byte of register rD, into the memory location that results from adding the contents of register rA and the value IMM, sign-extended to 32 bits.
Page 243 0-15 of rD. Bits 16-31 in rA will be copied into bits 16-31 of rD. Pseudocode ← (rD)[0:15] (rA)[16] ← (rD)[16:31] (rA)[16:31] Registers Altered • Latency • 1 cycle MicroBlaze Processor Reference Guide www.xilinx.com Send Feedback UG081 (v14.7)
Page 244 Chapter 5: MicroBlaze Instruction Set Architecture sext8 Sign Extend Byte sext8 rD, rA 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 Description This instruction sign-extends a byte (8 bits) into a word (32 bits). Bit 24 in rA will be copied into bits 0-23 of rD.
Page 245 ESR[W], ESR[Rx], if an unaligned data access exception is generated Latency • 1 cycle with C_AREA_OPTIMIZED=0 • 2 cycles with C_AREA_OPTIMIZED=1 Note The halfword reversed instruction is only valid if MicroBlaze is configured to use reorder instructions (C_USE_REORDER_INSTR = 1). MicroBlaze Processor Reference Guide www.xilinx.com Send Feedback UG081 (v14.7)
Page 246 Chapter 5: MicroBlaze Instruction Set Architecture Store Halfword Immediate rD, rA, IMM 1 1 1 1 0 1 Description Stores the contents of the least significant halfword of register rD, into the halfword aligned memory location that results from adding the contents of register rA and the value IMM, sign-extended to 32 bits.
Page 247 Carry flag. Pseudocode ← (rD)[0] (rA)[0] ← (rD)[1:31] (rA)[0:30] ← MSR[C] (rA)[31] Registers Altered • • MSR[C] Latency • 1 cycle MicroBlaze Processor Reference Guide www.xilinx.com Send Feedback UG081 (v14.7)
Page 248 Chapter 5: MicroBlaze Instruction Set Architecture Shift Right with Carry rD, rA 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 Description Shifts the contents of register rA, one bit to the right, and places the result in rD. The Carry flag is shifted in the shift chain and placed in the most significant bit of rD.
Page 249 The least significant bit coming out of the shift chain is placed in the Carry flag. Pseudocode ← (rD)[0] ← ( (rD)[1:31] rA)[0:30] ← MSR[C] (rA)[31] Registers Altered • • MSR[C] Latency • 1 cycle MicroBlaze Processor Reference Guide www.xilinx.com Send Feedback UG081 (v14.7)
Page 250 ESR[W], ESR[Rx], if an unaligned data access exception is generated Latency • 1 cycle with C_AREA_OPTIMIZED=0 • 2 cycles with C_AREA_OPTIMIZED=1 Note The word reversed instruction is only valid if MicroBlaze is configured to use reorder instructions (C_USE_REORDER_INSTR = 1). www.xilinx.com MicroBlaze Processor Reference Guide Send Feedback UG081 (v14.7)
Page 251 (rA)[8:15] ← (rD)[8:15] (rA)[16:23] ← (rD)[0:7] (rA)[24:31] Registers Altered • Latency • 1 cycle Note This instruction is only valid if MicroBlaze is configured to use reorder instructions (C_USE_REORDER_INSTR = 1). MicroBlaze Processor Reference Guide www.xilinx.com Send Feedback UG081 (v14.7)
Page 252 ← ( (rD)[0:15] rA)[16:31] ← ( (rD)[16:31] rA)[0:15] Registers Altered • Latency • 1 cycle Note This instruction is only valid if MicroBlaze is configured to use reorder instructions (C_USE_REORDER_INSTR = 1). www.xilinx.com MicroBlaze Processor Reference Guide Send Feedback UG081 (v14.7)
Page 253 This behavior can be overridden by preceding the Type B instruction with an imm instruction. See the instruction “imm,” page 204 for details on using 32-bit immediate values. MicroBlaze Processor Reference Guide www.xilinx.com Send Feedback UG081 (v14.7)
Page 254 Chapter 5: MicroBlaze Instruction Set Architecture Store Word Exclusive rD, rA, rB 1 1 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 Description Conditionally stores the contents of register rD, into the word aligned memory location that results from adding the contents of registers rA and rB.
Page 255 The carry flag (MSR[C]) may not be set immediately (dependent on pipeline stall behavior). The SWX instruction should not be immediately followed by an MSRCLR, MSRSET, MTS, or SRC instruction, to ensure the correct value of the carry flag is obtained. MicroBlaze Processor Reference Guide www.xilinx.com Send Feedback...
Page 256 E bit is not set. Register rA contains the address of the affected cache line, and the register rB value is not used. If the E bit is set to 1, MicroBlaze will request that the matching address in an external cache should be invalidated or flushed, depending on the value of the F bit.
Page 257 When using wdc.clear in a loop to invalidate a memory area in the cache, the loop can be optimized by using Ra as the memory area base address and Rb as the loop counter: addik r5,r0,memory_area_base_address addik r6,r0,memory_area_byte_size-C_DCACHE_LINE_LEN*4 loop: wdc.clear r5,r6 bgtid r6,loop addik r6,r6,-C_DCACHE_LINE_LEN*4 MicroBlaze Processor Reference Guide www.xilinx.com Send Feedback UG081 (v14.7)
Page 258 Register rA contains the address of the affected cache line. When MicroBlaze is configured to use an MMU (C_USE_MMU >= 1) this instruction is privileged. This means that if the instruction is attempted in User Mode (MSR[UM] = 1) a Privileged Instruction exception occurs.
Page 259 The contents of register rA are XORed with the contents of register rB; the result is placed into register rD. Pseudocode ← ⊕ (rD) (rA) (rB) Registers Altered • Latency • 1 cycle MicroBlaze Processor Reference Guide www.xilinx.com Send Feedback UG081 (v14.7)
Page 260 Chapter 5: MicroBlaze Instruction Set Architecture xori Logical Exclusive OR with Immediate xori rD, rA, IMM 1 0 1 0 1 0 Description The IMM field is extended to 32 bits by concatenating 16 0-bits on the left. The contents of register rA are XOR’ed with the extended IMM field;...
Page 261: Appendix A: Additional Resources
Appendix A Additional Resources EDK Documentation The following documents are available in your EDK installation. You can also access the entire documentation set online at http://www.xilinx.com/ise/embedded/edk_docs.htm. Relevant individual documents are linked below. • EDK Concepts, Tools, and Techniques (UG683) Note: The accompanying design files are in edk_ctt.zip.
Page 262 MicroBlaze Processor Reference Guide Send Feedback UG081 (v14.7)

Xilinx MicroBlaze Reference Manual

Chapter 1: Introduction

Chapter 2: Microblaze Architecture

Chapter 3: Microblaze Signal Interface Description

Chapter 4: Microblaze Application Binary Interface

Chapter 5: Microblaze Instruction Set Architecture

Appendix A: Additional Resources

Quick Links

Need help?

Questions and answers

Related Manuals for Xilinx MicroBlaze

Summary of Contents for Xilinx MicroBlaze

Table of Contents