Xilinx MicroBlaze Reference Manual page 139

Table 3-1: Summary of MicroBlaze Core I/O (Cont'd)
Signal
M_AXI_DC_ARLOCK
M_AXI_DC_ARCACHE
M_AXI_DC_ARPROT
M_AXI_DC_ARQOS
M_AXI_DC_ARVALID
M_AXI_DC_ARREADY
M_AXI_DC_ARUSER
M_AXI_DC_ARDOMAIN
M_AXI_DC_ARSNOOP
M_AXI_DC_ARBAR
M_AXI_DC_RID
M_AXI_DC_RDATA
M_AXI_DC_RRESP
M_AXI_DC_RLAST
M_AXI_DC_RVALID
M_AXI_DC_RREADY
M_AXI_DC_RUSER
M_AXI_DC_RACK
M_AXI_DC_ACVALID
M_AXI_DC_ACADDR
M_AXI_DC_ACSNOOP
M_AXI_DC_ACPROT
M_AXI_DC_ACREADY
M_AXI_DC_CRREADY
M_AXI_DC_CRVALID
M_AXI_DC_CRRESP
M_AXI_DC_CDVALID
M_AXI_DC_CDREADY
M_AXI_DC_CDDATA
M_AXI_DC_CDLAST
M_AXI_IC_AWID
M_AXI_IC_AWADDR
M_AXI_IC_AWLEN
M_AXI_IC_AWSIZE
M_AXI_IC_AWBURST
MicroBlaze Processor Reference Guide
UG984 (v2018.2) June 21, 2018
Interface I/O
O Master Lock type
M_AXI_DC
Master Cache type
O
M_AXI_DC
O Master Protection type
M_AXI_DC
O Master Quality of Service
M_AXI_DC
Master Read address valid
O
M_AXI_DC
I Slave Read address ready
M_AXI_DC
O Master Read address user signals
M_AXI_DC
O Master Read address domain
M_ACE_DC
Master Read address snoop
O
M_ACE_DC
O Master Read address barrier
M_ACE_DC
I Slave Read ID tag
M_AXI_DC
Slave Read data
I
M_AXI_DC
I Slave Read response
M_AXI_DC
I Slave Read last
M_AXI_DC
I Slave Read valid
M_AXI_DC
Master Read ready
O
M_AXI_DC
I Slave Read user signals
M_AXI_DC
O Master Read acknowledge
M_ACE_DC
I Slave Snoop address valid
M_ACE_DC
Slave Snoop address
I
M_ACE_DC
I Slave Snoop address snoop
M_ACE_DC
I Slave Snoop address protection type
M_ACE_DC
Master Snoop ready
O
M_ACE_DC
I Slave Snoop response ready
M_ACE_DC
O Master Snoop response valid
M_ACE_DC
O Master Snoop response
M_ACE_DC
Master Snoop data valid
O
M_ACE_DC
I Slave Snoop data ready
M_ACE_DC
O Master Snoop data
M_ACE_DC
Master Snoop data last
O
M_ACE_DC
O Master Write address ID
M_AXI_IC
O Master Write address
M_AXI_IC
O Master Burst length
M_AXI_IC
Master Burst size
O
M_AXI_IC
O Master Burst type
M_AXI_IC
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Chapter 3: MicroBlaze Signal Interface Description
Description
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