Xilinx MicroBlaze Reference Manual page 44

Table 2-26: Processor Version Register 2 (PVR2)
Bits Name
0 DAXI
1 DLMB
2 IAXI
3 ILMB
4 IRQEDGE
5 IRQPOS
6 CEEXC
7 FREQ
8 Reserved
9 Reserved
10 ACE
11 AXI4DP
12 FSL
13 FSLEXC
14 MSR
15 PCMP
16 AREA
17 BS
18 DIV
19 MUL
20 FPU
21 MUL64
22 FPU2
23 IMPEXC
24 Reserved
25 OP0EXC
26 UNEXC
27 OPEXC
28 AXIDEXC
MicroBlaze Processor Reference Guide
UG984 (v2018.2) June 21, 2018
Description
Data side AXI4 or ACE in use
Data side LMB in use
Instruction side AXI4 or ACE in use
Instruction side LMB in use
Interrupt is edge triggered
Interrupt edge is positive
Generate bus exceptions for ECC
correctable errors in LMB memory
Select implementation to optimize
processor frequency
Use ACE interconnect
Data Peripheral AXI interface uses AXI4
protocol, with support for exclusive access
Use extended AXI4-Stream instructions
Generate exception for AXI4-Stream
control bit mismatch
Use msrset and msrclr instructions
Use pattern compare and CLZ instructions
Select implementation to optimize area
with lower instruction throughput
Use barrel shifter
Use divider
Use hardware multiplier
Use FPU
Use 64-bit hardware multiplier
Use floating-point conversion and square
root instructions
Allow imprecise exceptions for ECC errors
in LMB memory
Generate exception for 0x0 illegal opcode
Generate exception for unaligned data
access
Generate exception for any illegal opcode
Generate exception for M_AXI_D error
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Chapter 2: MicroBlaze Architecture
Value
C_D_AXI
C_D_LMB
C_I_AXI
C_I_LMB
C_INTERRUPT_IS_EDGE
C_EDGE_IS_POSITIVE
C_ECC_USE_CE_EXCEPTION
C_AREA_OPTIMIZED =2
(Frequency)
0
1
C_INTERCONNECT = 3 (ACE)
C_M_AXI_DP_EXCLUSIVE_
ACCESS
C_USE_EXTENDED_FSL_INSTR
C_FSL_EXCEPTION
C_USE_MSR_INSTR
C_USE_PCMP_INSTR
C_AREA_OPTIMIZED = 1 (Area)
C_USE_BARREL
C_USE_DIV
C_USE_HW_MUL > 0 (None)
C_USE_FPU > 0 (None)
C_USE_HW_MUL = 2 (Mul64)
C_USE_FPU = 2 (Extended)
C_IMPRECISE_EXCEPTIONS
0
C_OPCODE_0x0_ILLEGAL
C_UNALIGNED_EXCEPTIONS
C_ILL_OPCODE_EXCEPTION
C_M_AXI_D_BUS_EXCEPTION
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