Xilinx MicroBlaze Reference Manual page 101

Performance Counter Command Register
The Performance Counter Command Register (PCCMDR) is used to issue commands to
clear, start, stop, or sample all counters. This register is a write-only register. Issuing a read
request has no effect, and undefined data is read.
X-Ref Target - Figure 2-27
31
Table 2-44: Performance Counter Command Register (PCCMDR)
Bits Name
4 Clear
3 Start
2 Stop
1 Sample
0 Reset
Performance Counter Status Register
The Performance Counter Status Register (PCSR) reads the sampled status of the counters.
To read the status for all configured counters, the register should be read repeatedly for
each of the counters. This register is a read-only register. Issuing a write request to the register
does nothing.
Every time the register is read, the selected counter is incremented. By using the
Performance Counter Command Register, the selected counter can be reset to the first
counter again. See
X-Ref Target - Figure 2-28
31
MicroBlaze Processor Reference Guide
UG984 (v2018.2) June 21, 2018
Reserved
Figure 2-27: Performance Counter Command Register
Clear all counters to zero
Start counting configured events for all counters simultaneously
Stop counting all counters simultaneously
Sample status and values in all counters simultaneously for reading
Reset accessed counter to the first event counter for access using the
Performance Counter Control, Status, Read Data and Write Data
Figure 2-28 and Table
Reserved
Figure 2-28: Performance Counter Status Register
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Chapter 2: MicroBlaze Architecture
5
Description
2-45.
4 3 2 1 0
CLR STA
STOP SAM RES
X19763-091117
Reset Value
0
0
0
0
0
2 1 0
OF FULL
X19764-082517
101
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