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Xilinx ML403 Application Note

Xilinx ML403 Application Note

Reference system: opb iic using the ml403 evaluation platform
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XAPP979 (v1.0) February 26, 2007
Summary
Included
Systems
Required
Hardware/Tools
© 2007 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and further disclaimers are as listed at http://www.xilinx.com/legal.htm. PowerPC is
a trademark of IBM Inc. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or information "as is." By providing the design, code, or information as one possible implementation of this feature,
application, or standard, Xilinx makes no representation that this implementation is free from any claims of infringement. You are responsible for obtaining any rights you may
require for your implementation. Xilinx expressly disclaims any warranty whatsoever with respect to the adequacy of the implementation, including but not limited to any warranties
or representations that this implementation is free from claims of infringement and any implied warranties of merchantability or fitness for a particular purpose.
XAPP979 (v1.0) February 26, 2007
Reference System: OPB IIC Using the
R
ML403 Evaluation Platform
Author: Paul Glover, Ed Meinelt, Lester Sanders
This application note describes how to build a reference system for the On-Chip Peripheral Bus
Inter IC (OPB IIC) core using the IBM PowerPC™ 405 Processor (PPC405) based embedded
system in the ML403 Embedded Development Platform. The reference system is Base System
Builder (BSB) based.
An IIC primer is given and an OPB IIC register reference is provided. The Xilinx Microprocessor
Debugger (XMD) commands are used for verifying that the OPB IIC core operates correctly.
Several software projects illustrate how to configure the OPB IIC core, set up interrupts, and do
read and write operations. Some of the software projects interface the OPB IIC to the
MicroChip 24LC04B serial EEPROM with an IIC interface, while others interface to the
TotalPhase Aardvark Adapter, which provides IIC master and slave functionality. The procedure
for using ChipScope™ to analyze OPB IIC functionality is provided. The steps used to build a
Linux kernel using MontaVista are listed. Simulation output files for analyzing basic IIC
transactions are provided.
This application note includes one reference system:
www.xilinx.com/bvdocs/appnotes/xapp979.zip
The project name used in xapp979.zip is ml403_ppc_opb_iic.
Users must have the following tools, cables, peripherals, and licenses available and installed:
•
Xilinx EDK 8.2.02i
•
Xilinx ISE 8.2.03
•
Xilinx Download Cable (Platform Cable USB or Parallel Cable IV)
•
Monta Vista Linux v2.4 Development Kit
•
Modeltech ModelSim v6.1d
•
ChipScope v8.2
Application Note: Embedded Processing
www.xilinx.com
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Summary of Contents for Xilinx ML403

  • Page 1 IBM Inc. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice. NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or information "as is." By providing the design, code, or information as one possible implementation of this feature, application, or standard, Xilinx makes no representation that this implementation is free from any claims of infringement.
  • Page 2 Introduction Introduction This application note accompanies a reference system built on the ML403 development board. Figure 1 The system uses the embedded PowerPC (PPC) as the microprocessor and the OPB IIC core. IIC Primer Figure 2 The master is responsible for setting up transactions. This includes generating the clock on SCL and defining which slave is involved in the communication, with an address field, and...
  • Page 3 Figure 4: Data Transfer on the IIC Bus shows the data transfer on the IIC bus, beginning with the START condition and Acknowledgment signal from slave interrupt within slave Figure 5: Generic Data Transer on the IIC Bus www.xilinx.com Data Data Acknowledgment signal from receiver Byte complete;...
  • Page 4 The IIC bus is a multi-master bus. Masters Master 1 Master 2 Figure 7: Arbitration of two Masters Table 1 provides the address map of the ML403 XC4VFX12. This is in the www.xilinx.com Not acknowledge Acknowledge Clock pulse for...
  • Page 5 Reference System Specifics ML403 XC4VFX12 Address Map Table 1: ML403 XC4VSX12 System Address Map Peripheral PLB_DDR OPB UART16550 OPB INTC PLB BRAM OPB IIC OPB IIC Registers Table 2 Table 2: OPB IIC Registers Device Global Interrupt Enable Interrupt Status Register...
  • Page 6 Master reading from Slave. A “0” indicates Master writing to Slave. Bus Busy. This bit indicates the status of the IIC bus. This bit is set when a START condition is detected and cleared when a STOP condition is detected. www.xilinx.com Description Description...
  • Page 7 CR(1) = ’1’. provides a register description of the Interrupt Status register. Name TFHE NAAS TE/STC www.xilinx.com Description Description Transmit FIFO Half Empty Not Addressed as Slave Addressed as Slave Bus is not Busy...
  • Page 8 figure, double click on the OPB IIC core in the EDK System Assembly View.. Microchip 24LC04 The Microchip Technology 24LC04B-I/ST with 4-KB EEPROM is provided on the ML403 board to store non-volatile data. The EEPROM write protect is tied off on the board to disable its hardware write protect.
  • Page 9 ML403 Board According to the MicroChip 24L024B data sheet, the ML403 board has a low-level output current (IOL) of 3.0 mA at a VCC of 2.5v. The ML403 boards are shipped in the configuration Information shown in 10K Ohm R70 and R71resistors with 833 or 1K Ohm resistors. See Answer Record 24049 for additional information.
  • Page 10 ML403 Board Information The resistors are located on the board as shown in Figure X979_12_022307 Figure 12: ML40x Resistors XAPP979 (v1.0) February 26, 2007 www.xilinx.com...
  • Page 11 ML403 Board Information If additional IIC devices are connected to the bus via the expansion header as shown in Figure 32. The resistor values are dependent on the voltage. XAPP979 (v1.0) February 26, 2007 13, insert additional pull-up resistors on the external signals connected at pins 31 and...
  • Page 12 Figure 14 TotalPhase Aardvark Adapter In the reference design, the OPB IIC in the XC4VFX12 on the ML403 board interfaces to the IIC in the Aardvark Adapter. The Aardvark IIC/SPI Embedded Systems interface is a multi- functional host adapter. The Aardvark Control Center software interacts with the Aardvark Adapter.
  • Page 13 Interfacing to the OPB IIC on the ML403 Board to the Aardvark Adapter Figure 16 the XC4VFX12 on the ML403 board and the IIC in the Aardvark Adapter. Executing the Reference System using the Pre-Built Bitstream and the Compiled Software Applications To execute the system using files inside the ml403_ppc_opb_IIC/ready_for_download...
  • Page 14 4. Invoke XMD with Debug Launch XMD. 5. Download the executable by the following command. dow <path>/executable.elf Verifying the Reference Design with Xilinx Microprocessor Debugger After downloading the bitstream file, issue the following XMD commands to verify that the ML403 reference design is set up correctly.
  • Page 15 The IIC devices on the ML300/ML310/ML410 boards do not support the repeated start option. The ML403 OPB IIC is configured as a master and the Aardvark Adapter IIC is configured as a IIC slave. The OPB IIC writes the data to the Aardvark IIC in multiple transactions with the repeated start option enabled.
  • Page 16 The message is in transmit.txt, and is the sentence "Lester Figure 18: Slave Example shows the structure of the dynamic_eeprom project. Make the dynamic_eeprom Figure 19: Selecting the eeprom Software Project www.xilinx.com X979 18 012907 X979_19_012907...
  • Page 17 Connect a serial cable to the RS232C port on the ML403 board. Start up a HyperTerminal. Set Bits per second to 9600, Data bits to 8, Parity to None, and Flow Control to None, as shown in Figure From XPS, start XMD and enter rst.
  • Page 18 3. Run Start → Programs → ChipScope Pro → ChipScope Inserter 4. From ChipScope Inserter, run File → Open Project ii.cdc. Inserter setup GUI. XAPP979 (v1.0) February 26, 2007 Figure 22: ChipScope Inserter Setup www.xilinx.com Figure 22 shows the ChipScope X979_22_012907...
  • Page 19 DATA* signal names with the signal names specified in ChipScope Inserter, select File → Import and enter iic.cdc in the dialog box. XAPP979 (v1.0) February 26, 2007 shows the GUI for making net connections. Click Next to move to the Modify Figure 23: Making Net Connections in ChipScope Inserter www.xilinx.com X979_23_012907...
  • Page 20 12. Run XMD and/or GDB to activate the trigger patterns which cause ChipScope to display meaningful output. XAPP979 (v1.0) February 26, 2007 Figure 24: Setting Up the Chipscope Trigger Figure 24, the trigger setup is to trigger when gen_start is High. www.xilinx.com X979_24_022307...

  • Page 21: Linux Kernel

    $PATH. 2. Change to the ml403_IIC/linux directory. 3. Run tar cf - -C /opt/montavista/pro/devkit/lsp/xilinx-ml300- ppc_405/linux-2.4.20_mvl31/ . tar xf - 4. To generate the Linux LSP in XPS, enter Software → Software Platform Settings. Select Kernel and Operating Systems, then select linux_mvl31 v1.00.c.
  • Page 22 Linux Kernel 5. Under OS and Libraries, set the entries as shown in Verify that the target directory is the same as the directory containing the Linux source. XAPP979 (v1.0) February 26, 2007 Figure Figure 26: BSP Settings www.xilinx.com X979_26_012907...
  • Page 23 Enable IIC. Disable PS/2 keyboard. Change to /dev/ram for booting from ramdisk. • Select Input Core Support. Disable all. • Select Character Devices. Disable Virtual. Leave Serial enabled. Disable Xilinx GPIO and Touchscreen. 10. Run make clean dep zImage.initrd. Verify that the zImage.initrd.elf file is in the ml403_ppc_opb_iic/linux/arch/ppc/boot/images directory.
  • Page 24 Copy the ace file to a 64-512 MB CompactFlash (CF) card in a CompactFlash reader/writer. Remove the CF card from the CF reader/writer and insert it into the CompactFlash slot (J22) on the ML403 board. Power up the board. Simulation The ml403_ppc_opb_iic/simulation directory contains waveform log file, opb_iic.wlf, for...
  • Page 25 Addressed by general call IIC data for microprocessor New data received on IIC bus Transmit FIFO Empty IRQs SDA value when slave SDA value when master Stop condition needs to be generated Repeated start Tx underflow prevent www.xilinx.com IIC_AA X979_28_012907 Table...
  • Page 26 Simulation The simulation runs for 2000 ns as shown in shown in the following figures. XAPP979 (v1.0) February 26, 2007 Figure 29. There are 3 sections in the simulation, Figure 29: Complete Simulation www.xilinx.com X979_29_022307...
  • Page 27 IIC_AA is initially the bus master, with the write CR_AA 0x0d. XAPP979 (v1.0) February 26, 2007 Figure 30, the OPB IIC registers are read to verify the correct Figure 30: Arbitrartion Lost Test Simulation www.xilinx.com X979_30_022307...
  • Page 28 CR_AA 0x0D -- Enables AA as master (5.9us) write IPIER_20 0x01 write DTR_20 AA write CR_20 0x0D -- Enables 20 as master wait_for_intr(30) read IPISR 0xD3 -- Arbitration lost (260 us) write CR_20 0x01 -- Clears interrupt Figure 31: Arbitration Lost Test Code www.xilinx.com X979_31_012907...
  • Page 29 55 from 20. The following stimuli / results is seen in the opb_iic.wlf file. XAPP979 (v1.0) February 26, 2007 Figure 32, runs from 575 s to 790 s . , Ths master, AA, receives 3C Figure 32: Simulation with iic_AA as Master www.xilinx.com X979_32_022307...
  • Page 30 SR_AA 0x8C read ISR_AA 0xCA -- TXER, DFF Full write CR_AA 0x41 read DRR_AA 0x55 (787 us) write ISR_AA 0xC8 write IRE_AA 0x10 -- Enable Bus is not Busy wait_for_intr Figure 33: Test code with iic_AA as Master www.xilinx.com X979_33_012907...
  • Page 31 Figure 34 master writing to IIC_AA, which is a 10-bit slave. XAPP979 (v1.0) February 26, 2007 shows the third test shown in opb_iic.wlf, run from 800 - 2000 us. IIC_20 is the Figure 34: Simulation with iic_AA as Master www.xilinx.com X979_34_012907...
  • Page 32 SR_20 0x0C -- SRW, BB XAPP979 (v1.0) February 26, 2007 provides the test code for simulation with IIC_AA as master. Figure 35: Test Code for Simulation with iic_20 as Master www.xilinx.com write DTR_20 0xA5 write DTR_20 0x96 write DTR_20 0x87...

  • Page 33: Revision History

    ML40x Embedded Development Platform User Guide UG080 (v2.5) May 24, 2006 ChipScope ILA Tools Tutorial The IIC Bus Specification Version 2.1 January 2000 Philips Semiconductors Revision The following table shows the revision history for this document. History Date 2/26/07 XAPP979 (v1.0) February 26, 2007 Version Initial Xilinx release. www.xilinx.com Revision...

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