Xilinx MicroBlaze Reference Manual page 276

rtid Return from Interrupt
rA, IMM
rtid
1 0 1 1 0 1 1 0 0 0 1
0
6
Description
Return from interrupt will branch to the location specified by the contents of rA plus the IMM field,
sign-extended to 32 bits. It will also enable interrupts after execution.
This instruction always has a delay slot. The instruction following the RTID is always executed before
the branch target. That delay slot instruction has interrupts disabled.
When MicroBlaze is configured to use an MMU (C_USE_MMU >= 1) this instruction is privileged. This
means that if the instruction is attempted in User Mode (MSR[UM] = 1) a Privileged Instruction
exception occurs.
With low-latency interrupt mode (C_USE_INTERRUPT = 2), the Interrupt_Ack output port is set to 10
when this instruction is executed, and subsequently to 11 when the MSR{IE] bit is set.
Pseudocode
if MSR[UM] = 1 then
←
ESR[EC]
else
←
(rA) + sext(IMM)
PC
Interrupt_Ack
allow following instruction to complete execution
←
MSR[IE]
←
MSR[UM]
←
MSR[VM]
Interrupt_Ack
Registers Altered
• PC
• MSR[IE], MSR[UM], MSR[VM]
• ESR[EC], in case a privileged instruction exception is generated
Latency
• 2 cycles
Notes
Convention is to use general purpose register r14 as rA.
A delay slot must not be used by the following: imm, branch, or break instructions. Interrupts and
external hardware breaks are deferred until after the delay slot branch has been completed.
MicroBlaze Processor Reference Guide
UG984 (v2018.2) June 21, 2018
rA
11
00111
←
10
1
MSR[UMS]
MSR[VMS]
←
11
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Chapter 5: MicroBlaze Instruction Set Architecture
IMM
16 31
277
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