Xilinx MicroBlaze Reference Manual page 124

Use Cases
Several common use cases are described here. These use cases are derived from the
LogiCore IP Processor LMB BRAM Interface Controller Product Guide (PG112)
Minimal
This system is obtained when enabling fault tolerance in MicroBlaze, without doing any
other configuration.
The system is suitable when area constraints are high, and there is no need for testing of the
ECC function, or analysis of error frequency and location. No ECC registers are
implemented. Single bit errors are corrected by the ECC logic before being passed to
MicroBlaze. Uncorrectable errors set an error signal, which generates an exception in
MicroBlaze.
Small
This system should be used when it is necessary to monitor error frequency, but there is no
need for testing of the ECC function. It is a minimal system with Correctable Error Counter
Register added to monitor single bit error rates. If the error rate is too high, the scrubbing
rate should be increased to minimize the risk of a single bit error becoming an
uncorrectable double bit error. Parameters set are
10.
Typical
This system represents a typical use case, where it is required to monitor error frequency, as
well as generating an interrupt to immediately correct a single bit error through software. It
does not provide support for testing of the ECC function.
It is a small system with Correctable Error First Failing registers and Status register added. A
single bit error will latch the address for the access into the Correctable Error First Failing
Address Register and set the
generated triggering MicroBlaze to read the failing address and then perform a read
followed by a write on the failing address. This will remove the single bit error from the
BRAM, thus reducing the risk of the single bit error becoming a uncorrectable double bit
error. Parameters set are:
= 1
- C_ECC
-
C_CE_COUNTER_WIDTH
-
C_ECC_STATUS_REGISTER
-
C_CE_FAILING_REGISTERS
MicroBlaze Processor Reference Guide
UG984 (v2018.2) June 21, 2018
C_ECC
bit in the ECC Status Register. An interrupt will be
CE_STATUS
= 10
= 1
= 1
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Chapter 2: MicroBlaze Architecture
[Ref
= 1 and
C_CE_COUNTER_WIDTH
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3].
=
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