Xilinx MicroBlaze Reference Manual page 218

brk Break
rD, rB
brk
1 0 0 1 1 0
0
6
Description
Branch and link to the instruction located at address value in rB. The current value of PC will be stored
in rD. The BIP flag in the MSR will be set, and the reservation bit will be cleared.
When MicroBlaze is configured to use an MMU (C_USE_MMU >= 1) this instruction is privileged. This
means that if the instruction is attempted in User Mode (MSR[UM] = 1) a Privileged Instruction
exception occurs.
Pseudocode
if MSR[UM] = 1 then
←
ESR[EC]
else
←
(rD) PC
←
PC (rB)
← 1
MSR[BIP]
Reservation
Registers Altered
• rD
• PC
• MSR[BIP]
• ESR[EC], in case a privileged instruction exception is generated
Latency
• 3 cycles
MicroBlaze Processor Reference Guide
UG984 (v2018.2) June 21, 2018
1 1 0 0
rD 0
11
00111
← 0
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Chapter 5: MicroBlaze Instruction Set Architecture
rB 0 0 0 0 0 0 0 0 0 0 0
16 21 31
219
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