Trace Interface Description - Xilinx MicroBlaze Reference Manual

Trace Interface Description

The MicroBlaze processor core exports a number of internal signals for trace purposes. This
signal interface is not standardized and new revisions of the processor might not be
backward compatible for signal selection or functionality. It is recommended that you not
design custom logic for these signals, but rather to use them using Xilinx provided analysis
IP. The trace signals are grouped in the TRACE bus. The current set of trace signals were last
updated for MicroBlaze v7.30 and are listed in
The mapping of the MSR bits is shown in
Machine Status Register, see
The Trace exception types are listed in
reserved.
Table 3-16: MicroBlaze Trace Signals
Signal Name
Trace_Valid_Instr
1
Trace_Instruction
1
Trace_PC
1
Trace_Reg_Write
1
Trace_Reg_Addr
1
Trace_MSR_Reg
1
Trace_PID_Reg
Trace_New_Reg_Value
Trace_Exception_Taken
Trace_Exception_Kind
1
Trace_Jump_Taken
1,3
Trace_Jump_Hit
1
Trace_Delay_Slot
1
Trace_Data_Access
1
Trace_Data_Address
Trace_Data_Write_Value
Trace_Data_Byte_Enable
MicroBlaze Processor Reference Guide
UG984 (v2018.2) June 21, 2018
"Special Purpose Registers" in Chapter
Description
Valid instruction on trace port.
Instruction code
Program counter
Instruction writes to the register file
Destination register address
Machine status register. The mapping
of the register bits is documented
below.
Process identifier register
Destination register update value
1
Instruction result in taken exception
1,2
Exception type. The description for the
1
exception type is documented below.
Branch instruction evaluated true, that
is taken
Branch Target Cache hit
Instruction is in delay slot of a taken
branch
Valid D-side memory access
Address for D-side memory access,
where N = 32 - 64, determined by
parameter C_ADDR_SIZE
Value for D-side memory write access
1
Byte enables for D-side memory access
1
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Chapter 3: MicroBlaze Signal Interface Description
Table 3-16.
Table 3-17. For a complete description of the
Table 3-18. All unused Trace exception types are
std_logic_vector (0 to 31)
std_logic_vector (0 to 31)
std_logic_vector (0 to 4)
std_logic_vector (0 to 14)
std_logic_vector (0 to 7)
std_logic_vector (0 to 31)
std_logic_vector (0 to 4)
std_logic_vector (0 to N-1)
std_logic_vector (0 to 31)
std_logic_vector (0 to 3)
2.
VHDL Type Direction
std_logic output
output
output
std_logic output
output
1
output
output
output
std_logic output
2
output
std_logic output
std_logic output
output
std_logic
output
std_logic
output
output
output
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