Privileged Instructions - Xilinx MicroBlaze Reference Manual

MicroBlaze has a single cycle latency for accesses to local memory (LMB) and for cache read
hits, except with
cache read hits require two clock cycles, and with
writes and halfword writes to LMB normally require two clock cycles.
The data cache write latency depends on
C_DCACHE_USE_WRITEBACK
cache needs to do memory accesses). When
write latency normally is two cycles (more if the posted-write buffer in the memory
controller is full).
The MicroBlaze instruction and data caches can be configured to use 4, 8 or 16 word cache
lines. When using a longer cache line, more bytes are prefetched, which generally improves
performance for software with sequential access patterns. However, for software with a
more random access pattern the performance can instead decrease for a given cache size.
This is caused by a reduced cache hit rate due to fewer available cache lines.
For details on the different memory interfaces, see
Description.

Privileged Instructions

The following MicroBlaze instructions are privileged:
• ,
GET GETD,PUT,PUTD
• ,
WIC WDC
•
MTS, MTSE
• ,
MSRCLR MSRSET
•
BRK
• , ,
RTID RTBD
• (except when jumping to physical address
BRKI
C_BASE_VECTORS
• ,
SLEEP HIBERNATE
• ,
LBUEA LHUEA
Attempted use of these instructions when running in user mode causes a privileged
instruction exception. When setting the parameter
instructions
GET
when running in user mode.
MicroBlaze Processor Reference Guide
UG984 (v2018.2) June 21, 2018
set to 1 (Area), when data side accesses and data
C_AREA_OPTIMIZED
is set to 1, the write latency normally is one cycle (more if the
(except when explicitly allowed)
(except when only the C bit is affected)
RTED
+ 0x18)
,
SUSPEND
, , , ,
LWEA SBEA SHEA SWEA
, , , and
GETD PUT PUTD
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Chapter 2: MicroBlaze Architecture
C_FAULT_TOLERANT
C_DCACHE_USE_WRITEBACK
C_DCACHE_USE_WRITEBACK
Chapter 3, MicroBlaze Signal Interface
C_BASE_VECTORS
(except when explicitly allowed)
C_MMU_PRIVILEGED_INSTR
are not considered privileged, and can be executed
set to 1, when byte
. When
is cleared to 0, the
+ 0x8 or
to 1 or 3, the
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