Dynamic Phase Shift Interface In The Mmcm - Xilinx 7 Series User Manual

For example, if the fractional divide value is 2.125, then a static phase shift step is
360/(2.125 x 8) = 21.176 degrees.
Interpolated Fine Phase Shift in Fixed or Dynamic Mode in the MMCM
Interpolated fine phase shift (IFPS) mode in the MMCM has linear shift behavior
independent of the CLKOUT_DIVIDE value and the phase shift resolution only depends
on the VCO frequency. In this mode the output clocks can be rotated 360° round robin
in linear increments of
If the VCO runs at 600 MHz, then the phase resolution is approximately (rounded) 30 ps
and at 1.6 GHz is approximately (rounded) 11 ps.
The phase shift value can be programmed as a fixed value set during configuration or a
dynamic increment/decrement under application control after configuration. The
dynamic phase shift is controlled by the PS interface of the MMCME2_ADV. This
phase-shift mode equally affects all CLKOUT output clocks that are selected for this mode
by setting the USE_FINE_PS attribute to TRUE. In interpolated fine phase-shift mode, a
clock must always be connected to the PSCLK pin of the MMCM. Regardless of the
interpolated fine phase-shift mode (fixed or dynamic) a clock is in, the clock must always
be connected to the PSCLK pin of the MMCM. Each individual CLKOUT counter can
independently either select the interpolated phase shift, the previously described static
phase-shift mode, or none. Fractional divide is not allowed in either fixed or dynamic
interpolated fine phase-shift mode. Fixed or dynamic phase shifting of the feedback path
will result in a negative phase shift of all output clocks with respect to CLKIN. The
dynamic phase-shift interface can not be used when the phase-shift mode is set to fixed.

Dynamic Phase Shift Interface in the MMCM

The MMCME2_ADV primitive provides three inputs and one output for dynamic
fine-phase shifting. Each CLKOUT and the CLKFBOUT divider can be individually
selected for phase shifting. The attributes CLKOUT[0:6]_USE_FINE_PS and
CLKFBOUT_USE_FINE_PS select the output clocks to be dynamically phase shifted. The
dynamic phase-shift amount is common to all the output clocks selected.
The variable phase shift is controlled by the PSEN, PSINCDEC, PSCLK, and PSDONE
ports
CLKOUT_PHASE attribute. Most commonly, no initial phase shift is selected. The phase of
the MMCM output clock(s) increments/decrements according to the interaction of PSEN,
PSINCDEC, PSCLK, and PSDONE from the initial or previously performed dynamic
phase shift. PSEN, PSINCDEC, and PSDONE are synchronous to PSCLK. When PSEN is
asserted for one PSCLK clock period, a phase-shift increment/decrement is initiated.
When PSINCDEC is High, an increment is initiated and when PSINCDEC is Low, a
decrement is initiated. Each increment adds to the phase shift of the MMCM clock outputs
by 1/56th of the VCO period. Similarly, each decrement decreases the phase shift by 1/
56th of the VCO period. PSEN must be active for one PSCLK period. PSDONE is High for
exactly one clock period when the phase shift is complete. The number of PSCLK cycles is
deterministic. After initiating the phase shift by asserting PSEN and the completion of the
phase shift signaled by PSDONE, the MMCM output clocks gradually drift from their
original phase shift to an increment/decrement phase shift in a linear fashion. The
completion of the increment or decrement is signaled when PSDONE asserts High. After
PSDONE has pulsed High, another increment/decrement can be initiated. There is no
maximum phase shift or phase-shift overflow. An entire clock period (360 degrees) can
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7 Series FPGAs Clocking Resources User Guide
UG472 (v1.5) July 13, 2012
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56F
VCO
(Figure 3-7). After the MMCM locks, the initial phase is determined by the
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General Usage Description
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