Xilinx MicroBlaze Reference Manual page 75

to 1 and the cache is turned off, or if the MMU Inhibit Caching bit is set for the
address. In all other cases the response is ignored.
The instructions side local memory (ILMB) can only cause instruction bus exception
-
when either an uncorrectable error occurs in the LMB memory, as indicated by the
signal, or
IUE
in the LMB memory, as indicated by the
• Illegal Opcode Exception: The illegal opcode exception is caused by an instruction
with an invalid major opcode (bits 0 through 5 of instruction). Bits 6 through 31 of the
instruction are not checked. Optional processor instructions are detected as illegal if
not enabled. If the optional feature
opcode exception is also caused if the instruction is equal to 0x00000000.
• Data Bus Exception: The data bus exception is caused by errors when reading data
from memory or writing data to memory.
The data peripheral AXI4 interface (
-
response on
The data cache AXI4 interface (
-
- An error response on
-
OKAY
The exception can only occur when
cache is turned off, when an exclusive access using
MMU Inhibit Caching bit is set for the address. In all other cases the response is
ignored.
The data side local memory (DLMB) can only cause instruction bus exception when
-
either an uncorrectable error occurs in the LMB memory, as indicated by the
signal, or
LMB memory, as indicated by the
accesses, and for byte and halfword write accesses.
• Unaligned Exception: The unaligned exception is caused by a word access where the
address to the data bus has bits 30 or 31 set, or a half-word access with bit 31 set.
MicroBlaze Processor Reference Guide
UG984 (v2018.2) June 21, 2018
C_ECC_USE_CE_EXCEPTION
or
M_AXI_DP_RRESP
M_AXI_DC
M_AXI_DC_RRESP
response on
M_AXI_DC_RRESP
C_ECC_USE_CE_EXCEPTION
www.xilinx.com
Chapter 2: MicroBlaze Architecture
is set to 1 and a correctable error occurs
signal.
ICE
C_OPCODE_0x0_ILLEGAL
) exception is caused by an error
M_AXI_DP
.
M_AXI_DP_BRESP
) exception is caused by:
or
M_AXI_DC_BRESP
in case of an exclusive access using
C_DCACHE_ALWAYS_USED
LWX
is set to 1 and a correctable error occurs in the
signal. An error can occur for all read
DCE
is enabled, an illegal
,
LWX
is set to 1 and the
or is performed, or if the
SWX
Send Feedback
.
DUE
75