Lockstep Interface Description - Xilinx MicroBlaze Reference Manual

Lockstep Interface Description

The lockstep interface on MicroBlaze is designed to connect a master and one or more slave
MicroBlaze instances. The lockstep signals on MicroBlaze are listed in the following table.
Table 3-13: MicroBlaze Lockstep Signals
Signal Name
Lockstep_Master_Out
Lockstep_Slave_In
Lockstep_Out
The comparison signals provided by
Table 3-14: MicroBlaze Lockstep Comparison Signals
MB_Halted
MB_Error
IFetch
I_AS
Instr_Addr
Data_Addr
Data_Write
D_AS
Read_Strobe
Write_Strobe
Byte_Enable
M_AXI_IP_AWID
M_AXI_IP_AWADDR
M_AXI_IP_AWLEN
M_AXI_IP_AWSIZE
M_AXI_IP_AWBURST
M_AXI_IP_AWLOCK
M_AXI_IP_AWCACHE
M_AXI_IP_AWPROT
M_AXI_IP_AWQOS
M_AXI_IP_AWVALID
M_AXI_IP_WDATA
MicroBlaze Processor Reference Guide
UG984 (v2018.2) June 21, 2018
Description
Output with signals going from master to
slave MicroBlaze. Not connected on slaves.
Input with signals coming from master to
slave MicroBlaze. Not connected on
master.
Output with all comparison signals from
both master and slaves.
Lockstep_Out
Signal Name
www.xilinx.com
Chapter 3: MicroBlaze Signal Interface Description
std_logic
std_logic
std_logic
are listed in the following table.
Bus Index Range
0
1
2
3
4 to 67
68 to 131
132 to 163
196
197
198
199 to 202
207
208 to 271
272 to 279
280 to 282
283 to 284
285
286 to 289
290 to 292
293 to 296
297
298 to 329
VHDL Type Direction
output
input
output
VHDL Type
std_logic
std_logic
std_logic
std_logic
std_logic_vector
std_logic_vector
std_logic_vector
std_logic
std_logic
std_logic
std_logic_vector
std_logic
std_logic_vector
std_logic_vector
std_logic_vector
std_logic_vector
std_logic
std_logic_vector
std_logic_vector
std_logic_vector
std_logic
std_logic_vector
164
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