Xilinx MicroBlaze Reference Manual page 238

Pseudocode
if MSR[UM] = 1 then
←
ESR[EC]
else
←
x rB[28:31]
if x >= C_FSL_LINKS then
←
x 0
←
(rD) Sx_AXIS_TDATA
if (n = 1) then
MSR[Carry]
if Sx_AXIS_TLAST
MSR[FSL]
if (e = 1) then
ESR[EC]
ESR[ESS]
EDR
Registers Altered
• rD, unless an exception is generated, in which case the register is unchanged
• MSR[FSL]
• MSR[Carry]
• ESR[EC], in case a stream exception or a privileged instruction exception is generated
• ESR[ESS], in case a stream exception is generated
• EDR, in case a stream exception is generated
Latency
• 1 cycle with
• 2 cycles with
The blocking versions of this instruction will stall the pipeline of MicroBlaze until the instruction can
be completed. Interrupts are served unless the instruction is atomic, which ensures that the
instruction cannot be interrupted.
Notes
The blocking versions of this instruction should not be placed in a delay slot, since this prevents
interrupts from being served.
For non-blocking versions, an rsubc instruction can be used to decrement an index variable.
The 'e' bit does not have any effect unless C_FSL_EXCEPTION is set to 1.
These instructions are only available when the MicroBlaze parameter C_FSL_LINKS is greater than 0
and the parameter C_USE_EXTENDED_FSL_INSTR is set to 1.
It is not recommended to allow these instructions in user mode, unless absolutely necessary for
performance reasons, since that removes all hardware protection preventing incorrect use of a link.
MicroBlaze Processor Reference Guide
UG984 (v2018.2) June 21, 2018
00111
←
Sx_AXIS_TVALID
≠
c and Sx_AXIS_TVALID then
←
1
←
00000
←
rB[28:31]
←
Sx_AXIS_TDATA
=0 or 2
C_AREA_OPTIMIZED
=1
C_AREA_OPTIMIZED
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Chapter 5: MicroBlaze Instruction Set Architecture
239
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