Xilinx MicroBlaze Reference Manual page 313

The F Margin System Methodology
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It is important to determine the IP performance in the context of a user system. In the case
of the MicroBlaze characterization, the system includes the following items:
• The IP under test (MicroBlaze Processor)
• Local Memory (LMB)
• One level of Interconnect (AXI4, AXI4-Lite, AXI4-Stream)
• Memory controller (EMC)
• On-chip BRAM controller
• Peripherals (UART, Timer, Interrupt Controller, MDM)
Determining the F
performance target.
The system above has three types of AXI Interconnect. AXI4-Lite used for peripheral
command and control, AXI4 used for memory accesses, and AXI4-Stream used for
MicroBlaze streams.
For F Margin System Analysis, the clock frequency of the system is incremented up to
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the maximum frequency where the system breaks with timing violations (worst case
negative slack). The reported frequency is the failing frequency subtracted with this worst
case negative slack.
Tool Options and Other Factors
Xilinx tools offer a number of options and settings that provide a trade-off between design
performance, resource usage, implementation run time, and memory footprint. The settings
that produce the best results for one design might not necessarily work for another design.
For the purpose of the F
default settings without specific constraints (other than the clocking constraint). This
analysis is done with all different FPGA architectures and the maximum speed grade.
MicroBlaze Processor Reference Guide
UG984 (v2018.2) June 21, 2018
of an Embedded IP with these components provides a more realistic
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Margin System Analysis, the IP design is characterized with
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Appendix A: Performance and Resource Utilization
314
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