Page 1 MicroBlaze Processor Reference Guide UG984 (v2018.2) June 21, 2018...
Page 2: Revision History
Describe bit field instructions, new in version 10.0. • Include information on parallel debug interface, new in version 10.0. • Added version 10.0 to MicroBlaze release version code in PVR. • Included Spartan-7 target architecture in PVR. • Updated description of MSR reset value.
Page 3 2015.1 • Included description of 16 word cache line length, new in version 9.5. • Added version 9.5 to MicroBlaze release version code in PVR. • Corrected description of supported endianness and parameter C_ENDIANNESS. • Corrected description of outstanding reads for instruction and data cache.
Page 4: Table Of Contents
MicroBlaze I/O Overview ........
Page 5 MicroBlaze Core Configurability ........
Page 6: Chapter 1: Introduction
Chapter 1 Introduction The MicroBlaze™ Processor Reference Guide provides information about the 32-bit soft processor, MicroBlaze, which is included in Vivado. The document is intended as a guide to the MicroBlaze hardware architecture. Guide Contents This guide contains the following chapters: •...
Page 7: Introduction
AXI4-Stream interfaces. Overview The MicroBlaze embedded processor soft core is a reduced instruction set computer (RISC) optimized for implementation in Xilinx® Field Programmable Gate Arrays (FPGAs). The following figure shows a functional block diagram of the MicroBlaze core.
Page 8 Chapter 2: MicroBlaze Architecture Features The MicroBlaze soft core processor is highly configurable, allowing you to select a specific set of features required by your design. The fixed feature set of the processor includes: • Thirty-two 32-bit general purpose registers •...
Page 9 Chapter 2: MicroBlaze Architecture Table 2-1: Configurable Feature Overview by MicroBlaze Version (Cont’d) MicroBlaze versions Feature v9.2 v9.3 v9.4 v9.5 v9.6 v10.0 Disable hardware multiplier option option option option option option Hardware debug readable ESR and Processor Version Register (PVR)
Page 10 Chapter 2: MicroBlaze Architecture Table 2-1: Configurable Feature Overview by MicroBlaze Version (Cont’d) MicroBlaze versions Feature v9.2 v9.3 v9.4 v9.5 v9.6 v10.0 Lockstep support option option option option option option Configurable use of FPGA option option option option option option...
Page 11: Data Types And Endianness
C_ENDIANNESS endian) by default. The hardware supported data types for MicroBlaze are word, half word, and byte. When using the reversed load and store instructions LHUR, LWR, SHR, and SWR, the bytes in the data are reversed, as indicated by the byte-reversed order.
Page 12: Instructions
Instructions Instruction Summary All MicroBlaze instructions are 32 bits and are defined as either Type A or Type B. Type A instructions have up to two source register operands and one destination register operand. Type B instructions have one source register and a 16-bit immediate operand (which can be extended to 32 bits by preceding the Type B instruction with an imm instruction).
Page 13 Operation performed on unsigned integer data type float Operation performed on floating-point data type clz(r) Count leading zeros Table 2-6: MicroBlaze Instruction Set Summary Type A 6-10 11-15 16-20 21-31 Semantics Type B...
Page 14 Chapter 2: MicroBlaze Architecture Table 2-6: MicroBlaze Instruction Set Summary (Cont’d) Type A 6-10 11-15 16-20 21-31 Semantics Type B 6-10 11-15 16-31 CMP Rd,Ra,Rb 000101 00000000001 Rd := Rb + Ra + 1 Rd[0] := 0 if (Rb >= Ra) else...
Page 15 Chapter 2: MicroBlaze Architecture Table 2-6: MicroBlaze Instruction Set Summary (Cont’d) Type A 6-10 11-15 16-20 21-31 Semantics Type B 6-10 11-15 16-31 TNCAPUTD Ra,Rb 010011 00000 0N1TA0 FSL Rb[28:31] := Ra (control write) 00000 MSR[C] := FSL_M_Full if N = 1...
Page 16 Chapter 2: MicroBlaze Architecture Table 2-6: MicroBlaze Instruction Set Summary (Cont’d) Type A 6-10 11-15 16-20 21-31 Semantics Type B 6-10 11-15 16-31 BSIFI Rd,Ra, 011001 10000 & M := (0xffffffff << (Imm + 1)) xor Width,Imm & 0 & Imm (0xffffffff <<...
Page 17 Chapter 2: MicroBlaze Architecture Table 2-6: MicroBlaze Instruction Set Summary (Cont’d) Type A 6-10 11-15 16-20 21-31 Semantics Type B 6-10 11-15 16-31 SEXT8 Rd,Ra 100100 0000000001100000 Rd := s(Ra[24:31]) SEXT16 Rd,Ra 100100 0000000001100001 Rd := s(Ra[16:31]) CLZ Rd, Ra...
Page 18 Chapter 2: MicroBlaze Architecture Table 2-6: MicroBlaze Instruction Set Summary (Cont’d) Type A 6-10 11-15 16-20 21-31 Semantics Type B 6-10 11-15 16-31 MTSE Sd,Ra 100101 01000 11 & Sd SPR[Sd} := Ra, where: · SPR[0x1003] is TLBLO[MSH] MFS Rd,Sa...
Page 19 Chapter 2: MicroBlaze Architecture Table 2-6: MicroBlaze Instruction Set Summary (Cont’d) Type A 6-10 11-15 16-20 21-31 Semantics Type B 6-10 11-15 16-31 BRK Rd,Rb 100110 01100 00000000000 PC := Rb Rd := PC MSR[BIP] := 1 BEQ Ra,Rb 100111...
Page 20 Chapter 2: MicroBlaze Architecture Table 2-6: MicroBlaze Instruction Set Summary (Cont’d) Type A 6-10 11-15 16-20 21-31 Semantics Type B 6-10 11-15 16-31 BRAID Imm 101110 00000 11000 PC := s(Imm) BRALID Rd,Imm 101110 11100 PC := s(Imm) Rd := PC...
Page 21 Chapter 2: MicroBlaze Architecture Table 2-6: MicroBlaze Instruction Set Summary (Cont’d) Type A 6-10 11-15 16-20 21-31 Semantics Type B 6-10 11-15 16-31 LWEA Rd,Ra,Rb 110010 00010000000 Addr := Ra & Rb Rd := *Addr SB Rd,Ra,Rb 110100 00000000000 Addr := Ra + Rb...
Page 22 For a semaphore operation to work properly, the LWX instruction must be paired with an SWX instruction, and both must specify identical addresses. The reservation granularity in MicroBlaze is a word. For both instructions, the address must be word aligned. No unaligned exceptions are generated for these instructions.
Page 23 Chapter 2: MicroBlaze Architecture • A conditional sequence begins with an LWX instruction. It can be followed by memory accesses and/or computations on the loaded value. The sequence ends with an SWX instruction. In most cases, failure of the SWX instruction should cause a branch back to the LWX for a repeated attempt.
Page 24 Chapter 2: MicroBlaze Architecture • The instructions to be modified could already have been fetched prior to modification: Into the instruction prefetch buffer Into the instruction cache, if it is enabled Into a stream buffer, if instruction cache stream buffers are used Into the instruction cache, and then saved in a victim buffer, if victim buffers are used.
Page 25: Registers
Chapter 2: MicroBlaze Architecture Registers MicroBlaze has an orthogonal instruction set architecture. It has thirty-two 32-bit general purpose registers and up to eighteen 32-bit special purpose registers, depending on configured options. General Purpose Registers The thirty-two 32-bit General Purpose Registers are numbered R0 through R31. The register file is reset on bit stream download (reset value is 0x00000000).
Page 26: Special Purpose Registers
Chapter 2: MicroBlaze Architecture Special Purpose Registers Program Counter (PC) The program counter (PC) is the 32-bit address of the execution instruction. It can be read with an MFS instruction, but it cannot be written with an MTS instruction. When used with the MFS instruction the PC register is specified by setting Sa = 0x0000.
Page 27 Chapter 2: MicroBlaze Architecture Table 2-9: Machine Status Register (MSR) Bits Name Description Reset Value Arithmetic Carry Copy Copy of the Arithmetic Carry (bit 29). CC is always the same as bit C. 1:16 Reserved Virtual Protected Mode Save Only available when configured with an MMU C_USE_MMU >...
Page 28 Chapter 2: MicroBlaze Architecture Table 2-9: Machine Status Register (MSR) (Cont’d) Bits Name Description Reset Value Exception Enable 0 = Hardware exceptions disabled 1 = Hardware exceptions enabled Only available if configured with exception support C_*_EXCEPTION or C_USE_MMU > 0 )
Page 29 Chapter 2: MicroBlaze Architecture Table 2-9: Machine Status Register (MSR) (Cont’d) Bits Name Description Reset Value Arithmetic Carry 0 = No Carry (Borrow) 1 = Carry (No Borrow) Read/Write Interrupt Enable 0 = Interrupts disabled 1 = Interrupts enabled Read/Write Reserved 1.
Page 30 Chapter 2: MicroBlaze Architecture Table 2-10: Exception Address Register (EAR) Bits Name Description Reset Value 0:C_ADDR_SIZE-1 Exception Address Register Exception Status Register (ESR) The Exception Status Register contains status bits for the processor. When read with the MFS instruction, the ESR is specified by setting Sa = 0x0005. The ESR register is illustrated...
Page 31 Chapter 2: MicroBlaze Architecture Table 2-11: Exception Status Register (ESR) (Cont’d) Bits Name Description Reset Value 27:31 Exception Cause 00000 = Stream exception 00001 = Unaligned data access exception 00010 = Illegal op-code exception 00011 = Instruction bus error exception...
Page 32 TLB miss Branch Target Register (BTR) The Branch Target Register only exists if the MicroBlaze processor is configured to use exceptions. The register stores the branch target address for all delay slot branch instructions executed while MSR[EIP] = 0. If an exception is caused by an instruction in a delay slot (that is, ESR[DS]=1), the exception handler should return execution to the address stored in BTR instead of the normal exception return address stored in R17.
Page 33 Chapter 2: MicroBlaze Architecture X-Ref Target - Figure 2-7 X19744-082517 Figure 2-7: BTR Table 2-13: Branch Target Register (BTR) Bits Name Description Reset Value 0:31 Branch target address used by handler when returning from 0x00000000 an exception caused by an instruction in a delay slot.
Page 34 Chapter 2: MicroBlaze Architecture Exception Data Register (EDR) The Exception Data Register stores data read on an AXI4-Stream link that caused a stream exception. The contents of this register is undefined for all other exceptions. When read with the MFS instruction, the EDR is specified by setting Sa = 0x000D.
Page 35 Chapter 2: MicroBlaze Architecture Table 2-16: Stack Low Register (SLR) Bits Name Description Reset Value 0:31 Stack Low Register 0x00000000 Stack High Register (SHR) The Stack High Register stores the stack high limit use to detect stack underflow. When the...
Page 36 Zone Protection Register (ZPR) The Zone Protection Register is used to override MMU memory protection defined in TLB entries. It is controlled by the configuration option on MicroBlaze. The register C_USE_MMU is only implemented if is greater than 1 (User Mode),...
Page 37 The Translation Look-Aside Buffer Low Register is used to access MMU Unified Translation Look-Aside Buffer (UTLB) entries. It is controlled by the configuration option on C_USE_MMU MicroBlaze. The register is only implemented if is greater than 1 (User Mode), C_USE_MMU is set to 0 (Performance) or 2 (Frequency). When accessed with the C_AREA_OPTIMIZED MFS and MTS instructions, the TLBLO is specified by setting Sa = 0x1003.
Page 38 Chapter 2: MicroBlaze Architecture X-Ref Target - Figure 2-14 C_ADDR_SIZE = 32 or C_USE_MMU ≠ 3: PAE: C_ADDR_SIZE > 32 and C_USE_MMU = 3 (n = C_ADDR_SIZE): n-10 ZSEL X19751-091317 Figure 2-14: TLBLO Table 2-20: Translation Look-Aside Buffer Low Register (TLBLO)
Page 39 The Translation Look-Aside Buffer High Register is used to access MMU Unified Translation Look-Aside Buffer (UTLB) entries. It is controlled by the configuration option on C_USE_MMU MicroBlaze. The register is only implemented if is greater than 1 (User Mode), C_USE_MMU is set to 0 (Performance) or 2 (Frequency). When accessed with the C_AREA_OPTIMIZED MFS and MTS instructions, the TLBHI is specified by setting Sa = 0x1004.
Page 40 Chapter 2: MicroBlaze Architecture The UTLB is not reset by the external reset inputs: Reset and Debug_Rst. Note: The following figure illustrates the TLBHI register and Table 2-21 provides bit descriptions and reset values. X-Ref Target - Figure 2-15 SIZE...
Page 41 The Translation Look-Aside Buffer Index Register is used as an index to the Unified Translation Look-Aside Buffer (UTLB) when accessing the TLBLO and TLBHI registers. It is controlled by the configuration option on MicroBlaze. The register is only C_USE_MMU implemented if...
Page 42 MSR[PVR]=0. • When is set to 1 (Basic), MicroBlaze implements only the first register: PVR0, and C_PVR if set to 2 (Full), all 13 PVR registers (PVR0 to PVR12) are implemented. When read with the MFS or MFSE instruction the PVR is specified by setting Sa = 0x200x, with x being the register number between 0x0 and 0xB.
Page 43 Chapter 2: MicroBlaze Architecture With extended data addressing is enabled (parameter > 32), the 32 least C_ADDR_SIZE significant bits of PVR8 and PVR9 are read with the MFS instruction, and the most significant bits with the MFSE instruction. When physical address extension (PAE) is enabled (parameters...
Page 44 Chapter 2: MicroBlaze Architecture Table 2-26: Processor Version Register 2 (PVR2) Bits Name Description Value DAXI Data side AXI4 or ACE in use C_D_AXI DLMB Data side LMB in use C_D_LMB IAXI Instruction side AXI4 or ACE in use C_I_AXI...
Page 45 Chapter 2: MicroBlaze Architecture Table 2-26: Processor Version Register 2 (PVR2) (Cont’d) Bits Name Description Value AXIIEXC Generate exception for M_AXI_I error C_M_AXI_I_BUS_EXCEPTION DIVEXC Generate exception for division by zero or C_DIV_ZERO_EXCEPTION division overflow FPUEXC Generate exceptions from FPU C_FPU_EXCEPTION...
Page 46 Chapter 2: MicroBlaze Architecture Table 2-28: Processor Version Register 4 (PVR4) Bits Name Description Value Use instruction cache C_USE_ICACHE ICTS Instruction cache tag size C_ADDR_TAG_BITS Reserved Allow instruction cache write C_ALLOW_ICACHE_WR 8:10 ICLL The base two logarithm of the instruction...
Page 47 Chapter 2: MicroBlaze Architecture Table 2-30: Processor Version Register 6 (PVR6) Bits Name Description Value 0:C_ADDR_SIZE-1 ICBA Instruction Cache Base Address C_ICACHE_BASEADDR Table 2-31: Processor Version Register 7 (PVR7) Bits Name Description Value 0:C_ADDR_SIZE-1 ICHA Instruction Cache High Address C_ICACHE_HIGHADDR...
Page 48 Chapter 2: MicroBlaze Architecture Table 2-35: Processor Version Register 11 (PVR11) Bits Name Description Value Use MMU: C_USE_MMU 0 = None 2 = Protection 1 = User Mode 3 = Virtual ITLB Instruction Shadow TLB size log2(C_MMU_ITLB_SIZE) DTLB Data Shadow TLB size...
Page 49: Pipeline Architecture
A control hazard occurs when a branch is taken, and the next instruction is not immediately available. This results in stalling the pipeline. MicroBlaze provides delay slot branches and the optional branch target cache to reduce the number of stall cycles.
Page 50 Chapter 2: MicroBlaze Architecture Three Stage Pipeline With set to 1 (Area), the pipeline is divided into three stages to C_AREA_OPTIMIZED minimize hardware cost: Fetch, Decode, and Execute. cycle1 cycle2 cycle3 cycle4 cycle5 cycle6 cycle7 instruction 1 Fetch Decode Execute...
Page 51 Chapter 2: MicroBlaze Architecture Eight Stage Pipeline With set to 2 (Frequency), the pipeline is divided into eight stages to C_AREA_OPTIMIZED maximize possible frequency: Fetch (IF), Decode (OF), Execute (EX), Access Memory 0 (M0), Access Memory 1 (M1), Access Memory 2 (M2), Access Memory 3 (M3) and Writeback (WB).
Page 52 Delay Slots When executing a taken branch with delay slot, only the fetch pipeline stage in MicroBlaze is flushed. The instruction in the decode stage (branch delay slot) is allowed to complete. This technique effectively reduces the branch penalty from two clock cycles to one. Branch instructions with delay slots have a D appended to the instruction mnemonic.
Page 53 Chapter 2: MicroBlaze Architecture clearing the BTC, the memory barrier or synchronizing branch should not be placed immediately after a branch instruction. There are three cases where the branch prediction can cause a mispredict, namely: • A conditional branch that should not have been taken, is actually taken, •...
Page 54 Chapter 2: MicroBlaze Architecture Avoiding Data Hazards In some cases, the MicroBlaze GNU Compiler is not able to optimize code to completely avoid data hazards. However, it is often possible to change the source code in order to achieve this, mainly by better utilization of the general purpose registers.
Page 55: Memory Architecture
The latter is necessary for software debugging. Both instruction and data interfaces of MicroBlaze are default 32 bits wide and use big endian or little endian, bit-reversed format, depending on the selected endianness.
Page 56: Privileged Instructions
(more if the posted-write buffer in the memory controller is full). The MicroBlaze instruction and data caches can be configured to use 4, 8 or 16 word cache lines. When using a longer cache line, more bytes are prefetched, which generally improves performance for software with sequential access patterns.
Page 57 Chapter 2: MicroBlaze Architecture It is strongly discouraged to do this, unless absolutely necessary for performance reasons, CAUTION! because it allows application processes to interfere with each other. When setting the parameter to 2 or 3, the extended address C_MMU_PRIVILEGED_INSTR...
Page 58: Virtual-Memory Management
Chapter 2: MicroBlaze Architecture Virtual-Memory Management Programs running on MicroBlaze use effective addresses to access a flat 4 GB address space. The processor can interpret this address space in one of two ways, depending on the translation mode: • In real mode, effective addresses are used to directly access physical memory •...
Page 59: Virtual Mode
Chapter 2: MicroBlaze Architecture Real Mode The processor references memory when it fetches an instruction and when it accesses data with a load or store instruction. Programs reference memory locations using a 32-bit effective address calculated by the processor. When real mode is enabled, the physical address is identical to the effective address and the processor uses it to access physical memory.
Page 60 Chapter 2: MicroBlaze Architecture Each address shown in Figure 2-18 contains a page-number field and an offset field. The page number represents the portion of the address translated by the MMU. The offset represents the byte offset into a page and is not translated by the MMU. The virtual address consists of an additional field, called the process ID (PID), which is taken from the PID register (see Process-ID Register, page 36).
Page 61 TLB. Translation Look-Aside Buffer The translation look-aside buffer (TLB) is used by the MicroBlaze MMU for address translation when the processor is running in virtual mode, memory protection, and storage control. Each entry within the TLB contains the information necessary to identify a virtual...
Page 62 Chapter 2: MicroBlaze Architecture • Data Shadow TLB: The DTLB contains data page-translation entries and is fully associative. The page-translation entries stored in the DTLB represent the most-recently accessed data-page translations from the UTLB. The DTLB is used to minimize contention between data translation and UTLB-update operations.
Page 63 Chapter 2: MicroBlaze Architecture TLB Entry Format The following figure shows the format of a TLB entry. Each TLB entry ranges from 68 bits up to 100 bits and is composed of two portions: TLBLO (also referred to as the data entry), and TLBHI (also referred to as the tag entry).
Page 64 Chapter 2: MicroBlaze Architecture Table 2-38: Page-Translation Bit Ranges by Page Size PAE Disabled PAE Enabled SIZE Page Tag Comparison Physical TLBHI Page Offset Bits Physical Page RPN Bits Size Bit Range Page Field Clear to Number Clear to 0...
Page 65 MMU are disabled. After system software initializes the UTLB with page-translation entries, management of the MicroBlaze UTLB is usually performed using interrupt handlers running in real mode. MicroBlaze Processor Reference Guide Send Feedback UG984 (v2018.2) June 21, 2018...
Page 66 Chapter 2: MicroBlaze Architecture The following figure diagrams the general process for examining a TLB entry. X-Ref Target - Figure 2-21 Check TLB-Entry Using Virtual Address TLB HI[V]=1 TLB Entry Miss TLBHI[TID]=0x00 Compare No Match TLB Entry Miss TLBHI[TID] with PID...
Page 67 Chapter 2: MicroBlaze Architecture Data-Storage Exception When virtual mode is enabled, (MSR[VM]=1), a data-storage exception occurs when access to a page is not permitted for any of the following reasons: • From user mode: The TLB entry specifies a zone field that prevents access to the page (ZPR[Zn]=00).
Page 68 Chapter 2: MicroBlaze Architecture Access Protection System software uses access protection to protect sensitive memory locations from improper access. System software can restrict memory accesses for both user-mode and privileged-mode software. Restrictions can be placed on reads, writes, and instruction fetches.
Page 69 Chapter 2: MicroBlaze Architecture Zone Protection Zone protection is used to override the access protection specified in a TLB entry. Zones are an arbitrary grouping of virtual pages with common access protection. Zones can contain any number of pages specifying any combination of page sizes. There is no requirement for a zone to contain adjacent pages.
Page 70 Solving the above problems in an efficient manner requires keeping track of page accesses and page modifications. MicroBlaze does not track page access and page modification in hardware. Instead, system software can use the TLB-miss exceptions and the data-storage exception to collect this information.
Page 71 Chapter 2: MicroBlaze Architecture The set write-protection bit serves as a record that a page has been modified. The data- storage handler can also record this information in a separate data structure associated with the page-translation entry. Tracking page modification is useful when virtual mode is first entered and when a new process is started.
Page 72: Reset, Interrupts, Exceptions, And Break
C_BASE_VECTORS The address range 0x28 to 0x4F is reserved for future software support by Xilinx. Allocating these addresses for user applications is likely to conflict with future releases of SDK support software.
Page 73 Illegal Instruction Exception, Data Storage Exception, Instruction Storage Exception, Data TLB Miss Exception, and Instruction TLB Miss Exception. A hardware exception causes MicroBlaze to flush the pipeline and branch to the hardware exception vector (address + 0x20). The execution stage instruction in the C_BASE_VECTORS exception cycle is not executed.
Page 74 Chapter 2: MicroBlaze Architecture • For all other exceptions the register R17 is loaded with the program counter value of the subsequent instruction, unless the exception is caused by an instruction in a branch delay slot. If the exception is caused by an instruction in a branch delay slot, the ESR[DS] bit is set.
Page 75 Chapter 2: MicroBlaze Architecture to 1 and the cache is turned off, or if the MMU Inhibit Caching bit is set for the address. In all other cases the response is ignored. The instructions side local memory (ILMB) can only cause instruction bus exception...
Page 76 MSR[EE] cleared), the pipeline is halted, and the external signal is set. MB_Error Imprecise Exceptions Normally all exceptions in MicroBlaze are precise, meaning that any instructions in the pipeline after the instruction causing an exception are invalidated, and have no effect. When is set to 1 (...
Page 77 C_BASE_VECTORS The break return address (the PC associated with the instruction in the decode stage at the time of the break) is automatically loaded into general purpose register R16. MicroBlaze also sets the Break In Progress ( ) flag in the Machine Status Register (MSR).
Page 78 MSR is not set. Latency The time it takes the MicroBlaze processor to enter a break service routine from the time the break occurs depends on the instruction currently in the execution stage and the latency to the memory storing the break vector.
Page 79 The address of each fast interrupt handler must be passed to the Interrupt Controller when initializing the interrupt system. When a particular interrupt occurs, this address is supplied by the Interrupt Controller, which allows MicroBlaze to directly jump to the handler code.
Page 80 Chapter 2: MicroBlaze Architecture Latency The time it takes MicroBlaze to enter an Interrupt Service Routine (ISR) from the time an interrupt occurs, depends on the configuration of the processor and the latency of the memory controller storing the interrupt vectors. If MicroBlaze is configured to have a hardware divider, the largest latency happens when an interrupt occurs during the execution of a division instruction.
Page 81: Instruction Cache
The cacheable instruction address consists of two parts: the cache address, and the tag address. The MicroBlaze instruction cache can be configured from 64 bytes to 64 kB. This corresponds to a cache address of between 6 and 16 bits. The tag address together with the cache address should match the full address of cacheable memory.
Page 82 8 kB and less for 4 word cache-lines, with 16 kB and less for 8 word cache- lines, and with 32 kB and less for 16 word cache-lines. For example: in a MicroBlaze configured with C_ICACHE_BASEADDR= 0x00300000...
Page 83 Chapter 2: MicroBlaze Architecture When is set to 1, a cache miss also occurs if a parity error is detected in C_FAULT_TOLERANT a tag or instruction Block RAM. The instruction cache issues burst accesses for the AXI4 interface when 32-bit data width is used, otherwise single accesses are used.
Page 84 Chapter 2: MicroBlaze Architecture WIC Instruction The optional WIC instruction ( ) is used to invalidate cache lines in C_ALLOW_ICACHE_WR=1 the instruction cache from an application. For a detailed description, see Chapter 5, MicroBlaze Instruction Set Architecture. The WIC instruction can also be used together with parity protection to periodically invalidate entries the cache, to avoid accumulating errors.
Page 85: Data Cache
Chapter 2: MicroBlaze Architecture Data Cache Overview The MicroBlaze processor can be used with an optional data cache for improved performance. The cached memory range must not include addresses in the LMB address range. The data cache has the following features: •...
Page 86: Data Cache Operation
The cacheable data address consists of two parts: the cache address, and the tag address. The MicroBlaze data cache can be configured from 64 bytes to 64 kB. This corresponds to a cache address of between 6 and 16 bits. The tag address together with the cache address should match the full address of cacheable memory.
Page 87 Chapter 2: MicroBlaze Architecture With the write-back protocol, a store to an address within the cacheable range always updates the cached data. If the target address word is not in the cache (that is, the access is a cache miss), and the location in the cache contains data that has not yet been written to memory (the cache location is dirty), the old data is written over the data AXI4 interface ) to external memory before updating the cache with the new data.
Page 88 Chapter 2: MicroBlaze Architecture The following table summarizes all types of accesses issued by the data cache AXI4 interface. Table 2-40: Data Cache Interface Accesses Policy State Direction Access Type Write- Cache Read Burst for 32-bit interface non-exclusive access and exclusive...
Page 89 The WDC instruction can also be used together with parity protection to periodically invalidate entries the cache, to avoid accumulating errors. With an external L2 cache, such as the System Cache, connected to MicroBlaze using the ACE interface, external cache invalidate or flush can be performed with WDC. See the...
Page 90: Floating-Point Unit (Fpu)
Chapter 2: MicroBlaze Architecture Floating-Point Unit (FPU) Overview The MicroBlaze floating-point unit is based on the IEEE 754-1985 standard[Ref 18]: • Uses IEEE 754 single precision floating-point format, including definitions for infinity, not-a-number (NaN), and zero • Supports addition, subtraction, multiplication, division, comparison, conversion and square root instructions •...
Page 91 X19761-082517 Figure 2-24: IEEE 754 Single Precision Format The value of a floating-point number v in MicroBlaze has the following interpretation: 1. If exponent = 255 and fraction <> 0, then v= NaN, regardless of the sign bit sign 2.
Page 92 The SDK compiler system, based on GCC, provides support for the floating-point Unit compliant with the MicroBlaze API. Compiler flags are automatically added to the GCC command line based on the type of FPU present in the system, when using SDK.
Page 93 Chapter 2: MicroBlaze Architecture Libraries and Binary Compatibility The SDK compiler system only includes software floating-point C runtime libraries. To take advantage of the hardware FPU, the libraries must be recompiled with the appropriate compiler switches. For all cases where separate compilation is used, it is very important that you ensure the consistency of FPU compiler flags throughout the build.
Page 94 Chapter 2: MicroBlaze Architecture The following not-recommended example calculates the sum of squares of the integers from 1 to 10 using floating-point representation: float sum, t; int i; sum = 0.0f; for (i = 1; i <= 10; i++) { t = (float)i;...
Page 95: Stream Link Interfaces
The interfaces on MicroBlaze are 32 bits wide. A separate bit indicates whether the sent/received word is of control or data type. The get instruction in the MicroBlaze ISA is used to transfer information from a port to a general purpose register. The put instruction is used to transfer data in the opposite direction.
Page 96: Debug And Trace
(commonly known as BDM or Background Debug Mode debuggers) like the Xilinx System Debugger (XSDB) tool. The debug interface is designed to be connected to the Xilinx Microprocessor Debug Module (MDM) core, which interfaces with the JTAG port of Xilinx FPGAs.
Page 97: Performance Monitoring
Chapter 2: MicroBlaze Architecture Performance Monitoring With extended debugging, MicroBlaze provides performance monitoring counters to count various events and to measure latency during program execution. The number of event counters and latency counters can be configured with C_DEBUG_EVENT_COUNTERS respectively, and the counter width can be set to 32, 48 or 64...
Page 98 Chapter 2: MicroBlaze Architecture A typical procedure to follow when initializing and using the performance monitoring counters is delineated in the steps below. 1. Initialize the events to be monitored: Use the Performance Command Register (Table 2-44) to reset the selected counter to the first counter, by setting the Reset bit.
Page 99 Chapter 2: MicroBlaze Architecture Table 2-41: MicroBlaze Performance Monitoring Events Event Description Event Description Event Counter Events Any valid instruction executed Floating-point (fadd, ..., fsqrt) Load word (lw, lwi, lwx) executed Number of clock cycles Load halfword (lhu, lhui) executed...
Page 100 MDM Debug Register Access Control DBG_CTRL Register to access the register, used with MDM software access to debug registers. Table 2-42: MicroBlaze Performance Monitoring Debug Registers DBG_CTRL Register Name Size (bits)
Page 101 Chapter 2: MicroBlaze Architecture Performance Counter Command Register The Performance Counter Command Register (PCCMDR) is used to issue commands to clear, start, stop, or sample all counters. This register is a write-only register. Issuing a read request has no effect, and undefined data is read.
Page 102 Chapter 2: MicroBlaze Architecture Table 2-45: Performance Counter Status Register (PCSR) Bits Name Description Reset Value Overflow This bit is set when the counter has counted past its maximum value This bit is set when a new latency counter event is started before the Full previous event has finished.
Page 103 Chapter 2: MicroBlaze Architecture Table 2-47: Performance Counter Data Items (Cont’d) Counter Type Item Description = 48 C_DEBUG_COUNTER_WIDTH Event Counter 31:16 0x0000 15:0 The number of times the event occurred, 16 most significant bits The number of times the event occurred, 32 least significant bits...
Page 104 Chapter 2: MicroBlaze Architecture Performance Counter Data Write Register The Performance Counter Data Write Register (PCDWR) writes initial values to the counters. To write all configured counters, the register should be written repeatedly. This register is a write-only register. Issuing a read request has no effect, and undefined data is read.
Page 105 Chapter 2: MicroBlaze Architecture Program and Event Trace With extended debugging, MicroBlaze provides program and event trace, either storing information in the Embedded Trace Buffer or transmitting it to the MDM, to enable program execution tracing. The MDM is used when the parameter...
Page 106 MDM Debug Register Access Control DBG_CTRL Register to access the register, used with MDM software access to debug registers. Table 2-49: MicroBlaze Program Trace Debug Registers DBG_CTRL Register Name Size (bits) Description...
Page 107 Chapter 2: MicroBlaze Architecture Trace Control Register The Trace Control Register (TCTRLR) is used to define the trace behavior. This register is a write-only register. Issuing a read request has no effect, and undefined data is read. See the following figure and table.
Page 108 Chapter 2: MicroBlaze Architecture Table 2-51: Trace Command Register (TCMDR) Bits Name Description Reset Value Clear Clear trace status and empty the trace buffer Start trace immediately Start Stop Stop trace immediately Sample Sample the number of current items in the trace buffer...
Page 109 Chapter 2: MicroBlaze Architecture Because a trace data entity can consist of more than 18 bits, depending on the compression level and stored data, the register might need to be read repeatedly to retrieve all information for a particular data entity. This is detailed in Table 2-54.
Page 110 11 – The item contains an event Cross-trigger event 15:1 10 – Cross-trigger event 13:8 Reserved Events according to “MicroBlaze Cross Trigger Events” defined in Table 2-63. Each event is represented by setting the corresponding bit in the bit field.
Page 111 2-55. value indicates the value to use in the MDM Debug Register Access Control DBG_CTRL Register to access the register, used with MDM software access to debug registers. Table 2-55: MicroBlaze Profiling Debug Registers DBG_CTRL Register Name Size (bits) Description...
Page 112 Chapter 2: MicroBlaze Architecture Profiling Control Register The Profiling Control Register (PCTRLR) is used to enable (start) profiling and disable (stop) profiling. It is also used to configure whether to count the number of executed instructions or the number of executed clock cycles, as well as define the Profiling Buffer bin usage.
Page 113 Chapter 2: MicroBlaze Architecture X-Ref Target - Figure 2-36 30 29 Reserved Low word address X19772-091117 Figure 2-36: Profiling Low Address Register Table 2-57: Profiling Low Address Register (PLAR) Bits Name Description Reset Value 29:0 Low word Low word address of the profiled area...
Page 114 Chapter 2: MicroBlaze Architecture Table 2-59: Profiling Buffer Address Register (PBAR) Bits Name Description Reset Value n-1:0 Buffer Bin in the Profiling Buffer to read or write. The number of bits (n) is 10 Address for a 4KB buffer, 11 for a 8KB buffer, …, 15 for a 128KB buffer.
Page 115 1, MicroBlaze will halt after a few instructions. XSDB DBG_STOP will detect that MicroBlaze has halted, and indicate where the halt occurred. The signal can be used to halt MicroBlaze at any external event, for example when a Vivado® Integrated Logic Analyzer (ILA) is triggered. •...
Page 116 Enable profiling Table 2-63: MicroBlaze Cross Trigger Events Number Event Description Generate an event when MicroBlaze is halted. The same event is signaled MicroBlaze halted when the MB_Halted output is set. Generate an event when the processor resumes execution from debug Execution resumed halt.
Page 117 Xilinx recommends that users only use the trace interface through Xilinx developed RECOMMENDED: analysis cores. This interface is not guaranteed to be backward compatible in future releases of MicroBlaze. Table 3-16 Chapter 3, MicroBlaze Signal Interface Description for a list of exported signals.
Page 118: Fault Tolerance
Configuration Using MicroBlaze Configuration You can enable Fault tolerance on the General page of the MicroBlaze configuration dialog box. After enabling fault tolerance in MicroBlaze, ECC is automatically enabled in the connected LMB BRAM Interface Controllers by the tools, when the system is generated. This means that nothing else needs to be configured to enable fault tolerance and minimal ECC support.
Page 119 MicroBlaze configuration dialog. This is not C_FAULT_TOLERANT recommended, unless no block RAM is used in MicroBlaze, and there is no need to handle bus exceptions from uncorrectable ECC errors. Features An overview of all MicroBlaze fault tolerance features is given here. Further details on each feature can be found in the following sections: •...
Page 120: Exception Handling
With fault tolerance enabled, if an error occurs in LMB block RAM, the LMB BRAM Interface Controller generates error signals on the LMB interface. If exceptions are enabled in the MicroBlaze processor by setting the EE bit in the Machine Status Register, the uncorrectable error signal either generates an instruction bus exception or a data bus exception, depending on the affected interface.
Page 121 LMB block RAM and all MicroBlaze internal block RAMs used in a particular configuration. This function is intended to be called periodically from a timer interrupt routine. One location of each block RAM is scrubbed every time it is called, using persistent data to track the current locations.
Page 122 The standalone BSP BRAM driver is used to access the ECC registers in the LMB BRAM Interface Controller, and also provides a comprehensive self test. By implementing the SDK Xilinx C Project "Peripheral Tests", a self-test example including the BRAM self test for each LMB BRAM Interface Controller in the system is generated.
Page 123 Chapter 2: MicroBlaze Architecture perform all possible tests of the ECC function. See the SDK help [Ref 9] for more information. The self-test example can be found in the standalone BSP BRAM driver source code, typically in the subdirectory microblaze_0/libsrc/bram_v3_03_a/src/xbram_selftest.c...
Page 124 LogiCore IP Processor LMB BRAM Interface Controller Product Guide (PG112) [Ref Minimal This system is obtained when enabling fault tolerance in MicroBlaze, without doing any other configuration. The system is suitable when area constraints are high, and there is no need for testing of the ECC function, or analysis of error frequency and location.
Page 125 Chapter 2: MicroBlaze Architecture Full This system uses all of the features provided by the LMB BRAM Interface Controller, to enable full error injection capability, as well as error monitoring and interrupt generation. It is a typical system with Uncorrectable Error First Failing registers and Fault Injection registers added.
Page 126: Lockstep Operation
Chapter 2: MicroBlaze Architecture Lockstep Operation MicroBlaze is able to operate in a lockstep configuration, where two or more identical MicroBlaze cores execute the same program. By comparing the outputs of the cores, any tampering attempts, transient faults or permanent hardware faults can be detected.
Page 127: Error Detection
Chapter 2: MicroBlaze Architecture The outputs from the master MicroBlaze core drive the peripherals in the system. All data leaving the protected area pass through inhibitors. Each inhibitor is controlled from its associated comparator. Each protected area of the design must be implemented in its own partition, using a hierarchical single chip cryptography (SCC) flow.
Page 128 MicroBlaze core drive the peripherals in the system. The slave MicroBlaze core only has inputs connected; all outputs are left open. The system contains the basic building block for designing a complete fault tolerant application, where one or more additional blocks must be added to provide redundancy.
Page 129: Coherency
Chapter 2: MicroBlaze Architecture Coherency MicroBlaze supports cache coherency, as well as invalidation of caches and translation look- aside buffers, using the AXI Coherency Extension (ACE) defined in AMBA® AXI and ACE Protocol Specification (Arm IHI 0022E) [Ref 15]. The coherency support is enabled when the parameter is set to 3 (ACE).
Page 130 Chapter 2: MicroBlaze Architecture After a MicroBlaze core has invalidated one or more entries, it must execute a memory barrier instruction (MBAR), to ensure that all peer processors have completed their TLB invalidation. • Branch Target Cache invalidation: When a MicroBlaze core in the coherency domain...
Page 131 Chapter 2: MicroBlaze Architecture Both interfaces issue the following subset of the possible Distributed Virtual Memory (DVM) transactions: • DVM Operation TLB Invalidate: Hypervisor TLB Invalidate by VA Branch Predictor Invalidate: L Branch Predictor Invalidate all Physical Instruction Cache Invalidate: Non-secure Physical Instruction Cache...
Page 132: Data And Instruction Address Extension
Chapter 2: MicroBlaze Architecture Data and Instruction Address Extension MicroBlaze has the ability to address up to 16EB of data controlled by the parameter , and also supports a physical instruction address up to 16EB when the MMU C_ADDR_SIZE Physical Address Extension (PAE) is enabled by setting = 3 (Virtual).
Page 133 Chapter 2: MicroBlaze Architecture The extended address load and store instructions are privileged when the MMU is enabled, unless they are allowed by setting the parameter C_MMU_PRIVILEGED_INSTR appropriately. If allowed, the instructions bypass the MMU translation treating the extended address as a physical address.
Page 134: Chapter 3: Microblaze Signal Interface Description
MicroBlaze™ processor. Overview The MicroBlaze core is organized as a Harvard architecture with separate bus interface units for data and instruction accesses. The following two memory interfaces are supported: Local Memory Bus (LMB), and the AMBA® AXI4 interface (AXI4) and ACE interface (ACE).
Page 135: Microblaze I/O Overview
Chapter 3: MicroBlaze Signal Interface Description MicroBlaze I/O Overview The core interfaces shown in the following figure and Table 3-1 are defined as follows: • M_AXI_DP: Peripheral Data Interface, AXI4-Lite or AXI4 interface • DLMB: Data interface, Local Memory Bus (BRAM only) •...
Page 136 Chapter 3: MicroBlaze Signal Interface Description Table 3-1: Summary of MicroBlaze Core I/O Signal Interface Description Master Write address ID M_AXI_DP_AWID M_AXI_DP Master Write address M_AXI_DP_AWADDR M_AXI_DP Master Burst length M_AXI_DP_AWLEN M_AXI_DP Master Burst size M_AXI_DP_AWSIZE M_AXI_DP Master Burst type...
Page 137 Chapter 3: MicroBlaze Signal Interface Description Table 3-1: Summary of MicroBlaze Core I/O (Cont’d) Signal Interface Description Slave Read valid M_AXI_DP_RVALID M_AXI_DP Master Read ready M_AXI_DP_RREADY M_AXI_DP Master Write address ID M_AXI_IP_AWID M_AXI_IP Master Write address M_AXI_IP_AWADDR M_AXI_IP Master Burst length...
Page 138 Chapter 3: MicroBlaze Signal Interface Description Table 3-1: Summary of MicroBlaze Core I/O (Cont’d) Signal Interface Description Slave Read response M_AXI_IP_RRESP M_AXI_IP Slave Read last M_AXI_IP_RLAST M_AXI_IP Slave Read valid M_AXI_IP_RVALID M_AXI_IP Master Read ready M_AXI_IP_RREADY M_AXI_IP Master Write address...
Page 139 Chapter 3: MicroBlaze Signal Interface Description Table 3-1: Summary of MicroBlaze Core I/O (Cont’d) Signal Interface Description Master Lock type M_AXI_DC_ARLOCK M_AXI_DC Master Cache type M_AXI_DC_ARCACHE M_AXI_DC Master Protection type M_AXI_DC_ARPROT M_AXI_DC Master Quality of Service M_AXI_DC_ARQOS M_AXI_DC Master Read address valid...
Page 140 Chapter 3: MicroBlaze Signal Interface Description Table 3-1: Summary of MicroBlaze Core I/O (Cont’d) Signal Interface Description Master Lock type M_AXI_IC_AWLOCK M_AXI_IC Master Cache type M_AXI_IC_AWCACHE M_AXI_IC Master Protection type M_AXI_IC_AWPROT M_AXI_IC Master Quality of Service M_AXI_IC_AWQOS M_AXI_IC Master Write address valid...
Page 141 Chapter 3: MicroBlaze Signal Interface Description Table 3-1: Summary of MicroBlaze Core I/O (Cont’d) Signal Interface Description Master Read address snoop M_AXI_IC_ARSNOOP M_ACE_IC Master Read address barrier M_AXI_IC_ARBAR M_ACE_IC Slave Read ID tag M_AXI_IC_RID M_AXI_IC Slave Read data M_AXI_IC_RDATA M_AXI_IC...
Page 142 Chapter 3: MicroBlaze Signal Interface Description Table 3-1: Summary of MicroBlaze Core I/O (Cont’d) Signal Interface Description ILMB Instruction interface LMB instruction fetch IFetch Instruction interface LMB read data bus ILMB Instr[0:31] ILMB Instruction interface LMB data ready IReady ILMB...
Page 143 = 2, for low-latency interrupt support. C_USE_INTERRUPT 2. MicroBlaze is a synchronous design clocked with the Clk signal, except for serial hardware debug logic, which is clocked with signal. If serial hardware debug logic is not used, there is no minimum frequency limit for .
Page 144 Hardware controlled by setting the input signal Pause to pause the pipeline. Software Controlled When an MBAR instruction is executed to enter sleep mode and MicroBlaze has completed all external accesses, the pipeline is halted and either the , or...
Page 145 This indicates to external hardware that it is safe to perform actions such as stopping the clock, resetting the processor or other IP cores. Different actions can be performed depending on which output signal is set. To wake up MicroBlaze when in sleep mode, one (or both) of the input signals must be set to one.
Page 146 Behavioral of clock_control is attribute X_INTERFACE_INFO : string; attribute X_INTERFACE_INFO of clkin : signal is "xilinx.com:signal:clock:1.0 clk CLK"; attribute X_INTERFACE_INFO of reset : signal is "xilinx.com:signal:reset:1.0 reset RST"; attribute X_INTERFACE_INFO of interrupt : signal is "xilinx.com:signal:interrupt:1.0 interrupt INTERRUPT";...
Page 147 IP cores. To continue from pause, the input signal must be cleared Pause to zero. In this case MicroBlaze continues instruction execution where it was previously paused. output signal from MicroBlaze indicates that the debugger requests the Dbg_Continue processor to continue from pause.
Page 148: Axi4 And Ace Interface Description
AXI4 and ACE Interface Description Memory Mapped Interfaces Peripheral Interfaces The MicroBlaze AXI4 memory mapped peripheral interfaces are implemented as 32-bit masters. Each of these interfaces only have a single outstanding transaction at any time, and all transactions are completed in order.
Page 149 This interface can have multiple outstanding transactions, either issuing up to 2 transactions when reading, or up to 32 transactions when writing. MicroBlaze ensures that all outstanding writes are completed before a read is issued, since the processor must maintain an ordered memory model but AXI4 or ACE has separate read/write channels without any ordering.
Page 150 Chapter 3: MicroBlaze Signal Interface Description Table 3-5: AXI Memory Mapped Interface Parameters (Cont’d) Interface Parameter Description 32: Default, single word accesses and burst accesses M_AXI_DC C_M_AXI_DC_DATA_WIDTH with C_DCACHE_LINE_LEN word busts used with AXI4 M_ACE_DC and ACE. Write bursts are only used with AXI4 when C_DCACHE_USE_WRITEBACK is set to 1.
Page 151 Chapter 3: MicroBlaze Signal Interface Description Values for access permissions, memory types, quality of service and shareability domain are defined in the following table. Table 3-6: AXI Interface Signal Definitions Interface Signal Description Access Permission: M_AXI_IP C_M_AXI_IP_ARPROT • Unprivileged, secure instruction access (100) if input signal Non_Secure[1] = 0 •...
Page 152 Write Operation A write to the stream interface is performed by MicroBlaze using one of the put or putd instructions. A write operation transfers the register contents to an output AXI4 interface. The transfer is completed in a single clock cycle for blocking mode writes (put and cput instructions) as long as the interface is not busy.
Page 153 Chapter 3: MicroBlaze Signal Interface Description Read Operation A read from the stream interface is performed by MicroBlaze using one of the get or getd instructions. A read operations transfers the contents of an input AXI4 interface to a general purpose register.
Page 154: Local Memory Bus (Lmb) Interface Description
1. N = 32 - 64, set according to parameter , added in MicroBlaze v9.6. C_ADDR_SIZE 2. N = 32 - 64, set according to parameter when PAE is enabled, added in MicroBlaze v10.0. C_ADDR_SIZE 3. Added in LMB for MicroBlaze v8.00 Addr[0:N-1] The address bus is an output from the core and indicates the memory address that is being accessed by the current transfer.
Page 155 Chapter 3: MicroBlaze Signal Interface Description Byte_Enable[0:3] The byte enable signals are outputs from the core and indicate which byte lanes of the data bus contain valid data. is valid only when AS is high. In multicycle Byte_Enable[0:3] accesses requiring more than one clock cycle to complete),...
Page 156 Data_Read[0:31] and halfword writes it indicates that the corresponding data word in local memory was erroneous before writing the new data. All operations on the LMB are synchronous to the MicroBlaze core clock. MicroBlaze Processor Reference Guide Send Feedback UG984 (v2018.2) June 21, 2018...
Page 157 Chapter 3: MicroBlaze Signal Interface Description LMB Transactions The following diagrams provide examples of LMB bus operations. Generic Write Operations X-Ref Target - Figure 3-4 Addr Byte_Enable Data_Write Read_Strobe Wirte_Strobe Data_Read Ready Don’t Care Wait X19788-091217 Figure 3-4: LMB Generic Write Operation, 0 Wait States...
Page 158 Chapter 3: MicroBlaze Signal Interface Description Generic Read Operations X-Ref Target - Figure 3-6 Addr Byte_Enable Data_Write Read_Strobe Wirte_Strobe Data_Read Ready Don’t Care Wait X19790-091217 Figure 3-6: LMB Generic Read Operation, 0 Wait States X-Ref Target - Figure 3-7 Addr...
Page 159 Chapter 3: MicroBlaze Signal Interface Description Back-to-Back Write Operation X-Ref Target - Figure 3-8 Addr Byte_Enable Data_Write Read_Strobe Wirte_Strobe Data_Read Ready Don’t Care Don’t Care Don’t Care Wait X19792-091217 Figure 3-8: LMB Back-to-Back Write Operation Back-to-Back Read Operation X-Ref Target - Figure 3-9...
Page 160 Chapter 3: MicroBlaze Signal Interface Description Back-to-Back Mixed Write/Read Operation X-Ref Target - Figure 3-10 Addr Byte_Enable Data_Write Read_Strobe Wirte_Strobe Data_Read Ready Don’t Care Wait X19794-091217 Figure 3-10: Back-to-Back Mixed Write/Read Operation, 0 Wait States X-Ref Target - Figure 3-11...
Page 161 • byte transfers to byte devices MicroBlaze does not support transfers that are larger than the addressed device. These types of transfers require dynamic bus sizing and conversion cycles that are not supported by the MicroBlaze bus interface. Data steering for read cycles are shown in...
Page 162 Other masters could have more restrictive requirements for byte lane placement than those Note: allowed by MicroBlaze. Slave devices are typically attached “left-justified” with byte devices attached to the most-significant byte lane, and halfword devices attached to the most significant halfword lane.
Page 163: Lockstep Interface Description
Chapter 3: MicroBlaze Signal Interface Description Lockstep Interface Description The lockstep interface on MicroBlaze is designed to connect a master and one or more slave MicroBlaze instances. The lockstep signals on MicroBlaze are listed in the following table. Table 3-13: MicroBlaze Lockstep Signals...
Page 164 Chapter 3: MicroBlaze Signal Interface Description Table 3-14: MicroBlaze Lockstep Comparison Signals (Cont’d) Signal Name Bus Index Range VHDL Type 362 to 365 std_logic_vector M_AXI_IP_WSTRB std_logic M_AXI_IP_WLAST std_logic M_AXI_IP_WVALID std_logic M_AXI_IP_BREADY std_logic M_AXI_IP_ARID 374 to 437 std_logic_vector M_AXI_IP_ARADDR 438 to 445...
Page 165 Chapter 3: MicroBlaze Signal Interface Description Table 3-14: MicroBlaze Lockstep Comparison Signals (Cont’d) Signal Name Bus Index Range VHDL Type std_logic M_AXI_DP_ARVALID std_logic M_AXI_DP_RREADY 723 + n * 35 std_logic Mn_AXIS_TLAST 758 + n * 35 to std_logic_vector Mn_AXIS_TDATA 789 + n * 35...
Page 166 Chapter 3: MicroBlaze Signal Interface Description Table 3-14: MicroBlaze Lockstep Comparison Signals (Cont’d) Signal Name Bus Index Range VHDL Type 2065 to 2068 std_logic_vector M_AXI_IC_ARSNOOP 2069 to 2070 std_logic_vector M_AXI_IC_ARBAR 2071 std_logic M_AXI_IC_RREADY 2072 std_logic M_AXI_IC_RACK 2073 std_logic M_AXI_IC_ACREADY 2074...
Page 167 Chapter 3: MicroBlaze Signal Interface Description Table 3-14: MicroBlaze Lockstep Comparison Signals (Cont’d) Signal Name Bus Index Range VHDL Type 2856 std_logic M_AXI_DC_ARVALID 2857 to 2861 std_logic_vector M_AXI_DC_ARUSER 2862 to 2863 std_logic_vector M_AXI_DC_ARDOMAIN 2864 to 2867 std_logic_vector M_AXI_DC_ARSNOOP 2868 to 2869...
Page 168: Debug Interface Description
Debug Module (MDM) IP core. The MDM is controlled by the Xilinx System Debugger (XSDB) through the JTAG port of the FPGA. The MDM can control multiple MicroBlaze processors at the same time. The debug signals are grouped in the DEBUG bus.
Page 169 DEBUG_ARESET 1. Updated for MicroBlaze v7.00: Dbg_Shift added and Debug_Rst included in DEBUG bus 2. Updated for MicroBlaze v9.3: Dbg_Trig signals added to DEBUG bus 3. Updated for MicroBlaze v9.4: External Program Trace signal added to DEBUG bus 4.
Page 170: Trace Interface Description
Chapter 3: MicroBlaze Signal Interface Description Trace Interface Description The MicroBlaze processor core exports a number of internal signals for trace purposes. This signal interface is not standardized and new revisions of the processor might not be backward compatible for signal selection or functionality. It is recommended that you not design custom logic for these signals, but rather to use them using Xilinx provided analysis IP.
Page 171 Chapter 3: MicroBlaze Signal Interface Description Table 3-16: MicroBlaze Trace Signals (Cont’d) Signal Name Description VHDL Type Direction D-side memory access is a read std_logic output Trace_Data_Read D-side memory access is a write output std_logic Trace_Data_Write Data memory address is within...
Page 172 Chapter 3: MicroBlaze Signal Interface Description Table 3-17: Mapping of Trace MSR Trace_MSR_Reg Machine Status Register Name Description Virtual Protected Mode Save Virtual Protected Mode User Mode Save User Mode Processor Version Register exists Exception In Progress Exception Enable Data Cache Enable...
Page 173: Microblaze Core Configurability
Chapter 3: MicroBlaze Signal Interface Description MicroBlaze Core Configurability The MicroBlaze core has been developed to support a high degree of user configurability. This allows tailoring of the processor to meet specific cost/performance requirements. Configuration is done using parameters that typically enable, size, or select certain processor features.
Page 174 Chapter 3: MicroBlaze Signal Interface Description Table 3-19: Configuration Parameters (Cont’d) Allowable Default Tool Parameter Name Feature/Description VHDL Type Values Value Assigned Generate exception for integer C_ECC_USE_CE_EXCEPTION correctable ECC error Lockstep Slave 0, 1 integer C_LOCKSTEP_SLAVE Disallow FPGA integer C_AVOID_PRIMITIVES...
Page 175 Chapter 3: MicroBlaze Signal Interface Description Table 3-19: Configuration Parameters (Cont’d) Allowable Default Tool Parameter Name Feature/Description VHDL Type Values Value Assigned Include hardware integer C_USE_DIV 0, 1 divider Include hardware integer C_USE_HW_MUL multiplier 0 = None 0, 1, 2...
Page 176 Chapter 3: MicroBlaze Signal Interface Description Table 3-19: Configuration Parameters (Cont’d) Allowable Default Tool Parameter Name Feature/Description VHDL Type Values Value Assigned Enable exception integer C_FPU_EXCEPTION handling for hardware 0, 1 floating-point unit exceptions Detect opcode 0x0 as an integer...
Page 177 Chapter 3: MicroBlaze Signal Interface Description Table 3-19: Configuration Parameters (Cont’d) Allowable Default Tool Parameter Name Feature/Description VHDL Type Values Value Assigned Trace Buffer size 0, 32, 64, C_DEBUG_TRACE_SIZE 128, 256, Embedded: 0, ≥ 8192 8192, External: 0, 32 - 8192...
Page 178 Chapter 3: MicroBlaze Signal Interface Description Table 3-19: Configuration Parameters (Cont’d) Allowable Default Tool Parameter Name Feature/Description VHDL Type Values Value Assigned Instruction cache integer C_ICACHE_ALWAYS_USED interface used for all 0, 1 memory accesses in the cacheable range Instruction cache tag...
Page 179 Chapter 3: MicroBlaze Signal Interface Description Table 3-19: Configuration Parameters (Cont’d) Allowable Default Tool Parameter Name Feature/Description VHDL Type Values Value Assigned Data cache write-back integer C_DCACHE_USE_WRITEBACK 0, 1 storage policy used Data cache victims 0, 2, 4, 8 integer...
Page 180 Chapter 3: MicroBlaze Signal Interface Description Table 3-19: Configuration Parameters (Cont’d) Allowable Default Tool Parameter Name Feature/Description VHDL Type Values Value Assigned Enable interrupt C_USE_INTERRUPT handling 0 = No interrupt 0, 1, 2 integer 1 = Standard interrupt 2 = Low-latency...
Page 181 Chapter 3: MicroBlaze Signal Interface Description Table 3-19: Configuration Parameters (Cont’d) Allowable Default Tool Parameter Name Feature/Description VHDL Type Values Value Assigned Data side AXI protocol AXI4, AXI4 string C_M_AXI_DP_PROTOCOL AXI4LITE LITE Data side AXI exclusive integer C_M_AXI_DP_ access support...
Page 182 Chapter 3: MicroBlaze Signal Interface Description Table 3-19: Configuration Parameters (Cont’d) Allowable Default Tool Parameter Name Feature/Description VHDL Type Values Value Assigned Data cache AXI protocol AXI4 AXI4 string C_M_AXI_DC_PROTOCOL Data cache AXI user integer C_M_AXI_DC_AWUSER_WIDTH width Data cache AXI user...
Page 183 Chapter 3: MicroBlaze Signal Interface Description Table 3-19: Configuration Parameters (Cont’d) Allowable Default Tool Parameter Name Feature/Description VHDL Type Values Value Assigned Instruction cache AXI integer C_M_AXI_IC_ARUSER_WIDTH user width Instruction cache AXI integer C_M_AXI_IC_WUSER_WIDTH user width Instruction cache AXI integer...
Page 184 Chapter 3: MicroBlaze Signal Interface Description Table 3-20: Parameter C_FAMILY Allowable Values Allowable Values Artix® aartix7 artix7 artix7l qartix7 qartix7l Kintex® kintex7 kintex7l qkintex7 qkintex7l kintexu kintexuplus Spartan® spartan7 Virtex® qvirtex7 virtex7 virtexu virtexuplus virtexuplusHBM Zynq® azynq zynq qzynq zynquplus zynquplusRFSOC...
Page 185: Introduction
Interrupt and Exception handling is also explained briefly. Data Types The data types used by MicroBlaze assembly programs are shown in the following table. Data types such as data8, data16, and data32 are used in place of the usual byte, half-word, and word.register.
Page 186: Register Usage Conventions
Chapter 4: MicroBlaze Application Binary Interface Register Usage Conventions The register usage convention for MicroBlaze is given in the following table. Table 4-2: Register Usage Conventions Register Type Enforcement Purpose Value 0 Dedicated Dedicated Stack Pointer Dedicated Read-only small data area anchor...
Page 187 Chapter 4: MicroBlaze Application Binary Interface The architecture for MicroBlaze defines 32 general purpose registers (GPRs). These registers are classified as volatile, non-volatile, and dedicated. • The volatile registers (also known as caller-save) are used as temporaries and do not retain values across the function calls.
Page 188: Stack Convention
Chapter 4: MicroBlaze Application Binary Interface Stack Convention The stack conventions used by MicroBlaze are detailed in Table 4-3. The shaded area in Table 4-3 denotes a part of the stack frame for a caller function, while the unshaded area indicates the callee frame function. The ABI conventions of the stack frame define the protocol for passing parameters, preserving non-volatile register values, and allocating space for the local variables in a function.
Page 189 Chapter 4: MicroBlaze Application Binary Interface Details of how the stack is maintained are shown in the following figure. X-Ref Target - Figure 4-1 High Memory Func 1 Func 1 Func 1 Func 1 Func 2 Func 2 Func 2...
Page 190: Memory Model
8 bytes in the MicroBlaze C compiler (mb-gcc), but this can be changed by giving a command line option to the compiler. Details about this option are discussed in the “GNU Compiler Tools” chapter...
Page 191: Interrupt, Break And Exception Handling
In this case, it is the responsibility of each handler to save and restore used registers. The MicroBlaze C compiler (mb-gcc) attribute fast_interrupt is available to allow this task to be performed by the compiler: void interrupt_handler_name() __attribute__((fast_interrupt));...
Page 192 The interrupt handler code starts with the label _interrupt_handler for interrupts that do not use low-latency handlers. In the current MicroBlaze system, there are dummy routines for interrupt, break and user exception handling, which you can change. In order to override these routines and link your own interrupt and exception handlers, you must define the handler code with specific attributes.
Page 193: Chapter 5: Microblaze Instruction Set Architecture
Chapter 5 MicroBlaze Instruction Set Architecture Introduction This chapter provides a detailed guide to the Instruction Set Architecture of the MicroBlaze™ processor. Notation The symbols used throughout this chapter are defined in the following table. Table 5-1: Symbol Notation Symbol...
Page 194 Chapter 5: MicroBlaze Instruction Set Architecture Table 5-1: Symbol Notation (Cont’d) Symbol Meaning < Less than comparison Less than or equal comparison <= Signal choice sext(x) Sign-extend x Memory location at address x Mem(x) FSLx AXI4-Stream interface x LSW(x) Least Significant Word of x...
Page 195: Formats
Instructions This section provides descriptions of MicroBlaze instructions. Instructions are listed in alphabetical order. For each instruction Xilinx provides the mnemonic, encoding, a description, pseudocode of its semantics, and a list of registers that it modifies. MicroBlaze Processor Reference Guide Send Feedback UG984 (v2018.2) June 21, 2018...
Page 196 Chapter 5: MicroBlaze Instruction Set Architecture Arithmetic Add rD, rA, rB addc Add with Carry rD, rA, rB addk rD, rA, rB Add and Keep Carry addkc Add with Carry and Keep Carry rD, rA, rB 0 0 0 K C 0...
Page 197 Chapter 5: MicroBlaze Instruction Set Architecture addi Arithmetic Add Immediate rD, rA, IMM addi Add Immediate addic rD, rA, IMM Add Immediate with Carry rD, rA, IMM addik Add Immediate and Keep Carry addikc rD, rA, IMM Add Immediate with Carry and Keep Carry...
Page 198 Chapter 5: MicroBlaze Instruction Set Architecture Logical AND rD, rA, rB 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 Description The contents of register rA are ANDed with the contents of register rB; the result is placed into register Pseudocode ←...
Page 199 Chapter 5: MicroBlaze Instruction Set Architecture andi Logial AND with Immediate rD, rA, IMM andi 1 0 1 0 0 1 Description The contents of register rA are ANDed with the value of the IMM field, sign-extended to 32 bits; the result is placed into register rD.
Page 200 Chapter 5: MicroBlaze Instruction Set Architecture andn Logical AND NOT rD, rA, rB andn 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 Description The contents of register rA are ANDed with the logical complement of the contents of register rB; the result is placed into register rD.
Page 201 Chapter 5: MicroBlaze Instruction Set Architecture andni Logical AND NOT with Immediate rD, rA, IMM andni 1 0 1 0 1 1 Description The IMM field is sign-extended to 32 bits. The contents of register rA are ANDed with the logical complement of the extended IMM field;...
Page 202 Chapter 5: MicroBlaze Instruction Set Architecture Branch if Equal rA, rB Branch if Equal beqd rA, rB Branch if Equal with Delay 1 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Description Branch if rA is equal to 0, to the instruction located in the offset value of rB.
Page 203 Chapter 5: MicroBlaze Instruction Set Architecture beqi Branch Immediate if Equal rA, IMM beqi Branch Immediate if Equal beqid rA, IMM Branch Immediate if Equal with Delay 1 0 1 1 1 1 0 0 0 0 Description Branch if rA is equal to 0, to the instruction located in the offset value of IMM. The target of the branch will be the instruction at address PC + IMM.
Page 204 Chapter 5: MicroBlaze Instruction Set Architecture Branch if Greater or Equal rA, rB Branch if Greater or Equal bged rA, rB Branch if Greater or Equal with Delay 1 0 0 1 1 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 Description Branch if rA is greater or equal to 0, to the instruction located in the offset value of rB.
Page 205 Chapter 5: MicroBlaze Instruction Set Architecture bgei Branch Immediate if Greater or Equal rA, IMM bgei Branch Immediate if Greater or Equal bgeid rA, IMM Branch Immediate if Greater or Equal with Delay 1 0 1 1 1 1 0 1 0 1 Description Branch if rA is greater or equal to 0, to the instruction located in the offset value of IMM.
Page 206 Chapter 5: MicroBlaze Instruction Set Architecture Branch if Greater Than rA, rB Branch if Greater Than bgtd rA, rB Branch if Greater Than with Delay 1 0 0 1 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 Description Branch if rA is greater than 0, to the instruction located in the offset value of rB.
Page 207 Chapter 5: MicroBlaze Instruction Set Architecture bgti Branch Immediate if Greater Than rA, IMM bgti Branch Immediate if Greater or Equal bgtid rA, IMM Branch Immediate if Greater or Equal with Delay 1 0 1 1 1 1 0 1 0 0 Description Branch if rA is greater than 0, to the instruction located in the offset value of IMM.
Page 208 Chapter 5: MicroBlaze Instruction Set Architecture Branch if Less or Equal rA, rB Branch if Less or Equal bled rA, rB Branch if Less or Equal with Delay 1 0 0 1 1 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 Description Branch if rA is less or equal to 0, to the instruction located in the offset value of rB.
Page 209 Chapter 5: MicroBlaze Instruction Set Architecture blei Branch Immediate if Less or Equal rA, IMM blei Branch Immediate if Less or Equal bleid rA, IMM Branch Immediate if Less or Equal with Delay 1 0 1 1 1 1 0 0 1 1 Description Branch if rA is less or equal to 0, to the instruction located in the offset value of IMM.
Page 210 Chapter 5: MicroBlaze Instruction Set Architecture Branch if Less Than rA, rB Branch if Less Than bltd rA, rB Branch if Less Than with Delay 1 0 0 1 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 Description Branch if rA is less than 0, to the instruction located in the offset value of rB.
Page 211 Chapter 5: MicroBlaze Instruction Set Architecture blti Branch Immediate if Less Than rA, IMM blti Branch Immediate if Less Than bltid rA, IMM Branch Immediate if Less Than with Delay 1 0 1 1 1 1 0 0 1 0 Description Branch if rA is less than 0, to the instruction located in the offset value of IMM.
Page 212 Chapter 5: MicroBlaze Instruction Set Architecture Branch if Not Equal rA, rB Branch if Not Equal bned rA, rB Branch if Not Equal with Delay 1 0 0 1 1 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 Description Branch if rA not equal to 0, to the instruction located in the offset value of rB.
Page 213 Chapter 5: MicroBlaze Instruction Set Architecture bnei Branch Immediate if Not Equal rA, IMM bnei Branch Immediate if Not Equal bneid rA, IMM Branch Immediate if Not Equal with Delay 1 0 1 1 1 1 0 0 0 1 Description Branch if rA not equal to 0, to the instruction located in the offset value of IMM.
Page 214 Chapter 5: MicroBlaze Instruction Set Architecture Unconditional Branch Branch Branch Absolute Branch with Delay brad Branch Absolute with Delay rD, rB brld Branch and Link with Delay brald rD, rB Branch Absolute and Link with Delay 1 0 0 1 1 0...
Page 215 Chapter 5: MicroBlaze Instruction Set Architecture Note The instructions brl and bral are not available. A delay slot must not be used by the following: imm, branch, or break instructions. Interrupts and external hardware breaks are deferred until after the delay slot branch has been completed.
Page 216 As a special case, when MicroBlaze is configured to use an MMU (C_USE_MMU >= 1) and “bralid rD, C_BASE_VECTORS+0x8“ is used to perform a User Vector Exception, the Machine Status Register bits User Mode and Virtual Mode are cleared.
Page 217 Chapter 5: MicroBlaze Instruction Set Architecture Registers Altered • • • MSR[UM], MSR[VM] Latency • 1 cycle (if successful branch prediction occurs) • 2 cycles (if the D bit is set) • 3 cycles (if the D bit is not set, or a branch prediction mispredict occurs with C_AREA_OPTIMIZED •...
Page 218 The BIP flag in the MSR will be set, and the reservation bit will be cleared. When MicroBlaze is configured to use an MMU (C_USE_MMU >= 1) this instruction is privileged. This means that if the instruction is attempted in User Mode (MSR[UM] = 1) a Privileged Instruction exception occurs.
Page 219 User Mode (MSR[UM] = 1) a Privileged Instruction exception occurs. As a special case, when MicroBlaze is configured to use an MMU (C_USE_MMU >= 1) and “brki rD, C_BASE_VECTORS+0x8” or “brki rD, C_BASE_VECTORS+0x18” is used to perform a Software Break, the Machine Status Register bits User Mode and Virtual Mode are cleared.
Page 220 Chapter 5: MicroBlaze Instruction Set Architecture Notes By default, Type B Instructions will take the 16-bit IMM field value and sign extend it to 32 bits to use as the immediate operand. This behavior can be overridden by preceding the Type B instruction with an imm instruction.
Page 221 =0 or 2 C_AREA_OPTIMIZED • 2 cycles with C_AREA_OPTIMIZED Note These instructions are optional. To use them, MicroBlaze has to be configured to use barrel shift instructions (C_USE_BARREL=1). MicroBlaze Processor Reference Guide Send Feedback UG984 (v2018.2) June 21, 2018 www.xilinx.com...
Page 222 Chapter 5: MicroBlaze Instruction Set Architecture Barrel Shift Immediate rD, rA, IMM bsrli Barrel Shift Right Logical Immediate bsrai rD, rA, IMM Barrel Shift Right Arithmetic Immediate rD, rA, IMM bslli Barrel Shift Left Logical Immediate bsefi rD, rA, IMM...
Page 223 Notes These are not Type B Instructions. There is no effect from a preceding imm instruction. These instructions are optional. To use them, MicroBlaze has to be configured to use barrel shift instructions (C_USE_BARREL=1). The assembler code “bsifi rD, rA, width, shift” denotes the actual bit field width, not the IMM...
Page 224 Chapter 5: MicroBlaze Instruction Set Architecture Count Leading Zeros rD, rA Count leading zeros in rA 1 0 0 1 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 Description This instruction counts the number of leading zeros in register rA starting from the most significant bit.
Page 225 Chapter 5: MicroBlaze Instruction Set Architecture Integer Compare rD, rA, rB compare rB with rA (signed) cmpu rD, rA, rB compare rB with rA (unsigned) 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 U 1...
Page 226 4 cycles with C_AREA_OPTIMIZED • 6 cycles with C_AREA_OPTIMIZED • 1 cycle with C_AREA_OPTIMIZED Note This instruction is only available when the MicroBlaze parameter C_USE_FPU is greater than 0. MicroBlaze Processor Reference Guide Send Feedback UG984 (v2018.2) June 21, 2018 www.xilinx.com...
Page 227 4 cycles with C_AREA_OPTIMIZED • 6 cycles with C_AREA_OPTIMIZED • 1 cycle with C_AREA_OPTIMIZED Note This instruction is only available when the MicroBlaze parameter C_USE_FPU is greater than 0. MicroBlaze Processor Reference Guide Send Feedback UG984 (v2018.2) June 21, 2018 www.xilinx.com...
Page 228 4 cycles with C_AREA_OPTIMIZED • 6 cycles with C_AREA_OPTIMIZED • 1 cycle with C_AREA_OPTIMIZED Note This instruction is only available when the MicroBlaze parameter C_USE_FPU is greater than 0. MicroBlaze Processor Reference Guide Send Feedback UG984 (v2018.2) June 21, 2018 www.xilinx.com...
Page 229 28 cycles with C_AREA_OPTIMIZED • 30 cycles with C_AREA_OPTIMIZED • 24 cycles with C_AREA_OPTIMIZED Note This instruction is only available when the MicroBlaze parameter C_USE_FPU is greater than 0. MicroBlaze Processor Reference Guide Send Feedback UG984 (v2018.2) June 21, 2018 www.xilinx.com...
Page 230 =0 or 2 C_AREA_OPTIMIZED • 3 cycles with C_AREA_OPTIMIZED Note These instructions are only available when the MicroBlaze parameter C_USE_FPU is greater than 0. Table 5-2 lists the floating-point comparison operations. MicroBlaze Processor Reference Guide Send Feedback UG984 (v2018.2) June 21, 2018...
Page 231 Chapter 5: MicroBlaze Instruction Set Architecture Table 5-2: Floating-Point Comparison Operation Comparison Type Operand Relationship isSigNaN(rA) or isQuietNaN(rA) or Description OpSel (rB) > (rA) (rB) < (rA) (rB) = (rA) isSigNaN(rB) isQuietNaN(rB) Unordered (rD) ← 0 (rD) ← 0 (rD) ←...
Page 232 4 cycles with C_AREA_OPTIMIZED • 6 cycles with C_AREA_OPTIMIZED • 1 cycle with C_AREA_OPTIMIZED Note This instruction is only available when the MicroBlaze parameter C_USE_FPU is set to 2 (Extended). MicroBlaze Processor Reference Guide Send Feedback UG984 (v2018.2) June 21, 2018 www.xilinx.com...
Page 233 5 cycles with C_AREA_OPTIMIZED • 7 cycles with C_AREA_OPTIMIZED • 2 cycles with C_AREA_OPTIMIZED Note This instruction is only available when the MicroBlaze parameter C_USE_FPU is set to 2 (Extended). MicroBlaze Processor Reference Guide Send Feedback UG984 (v2018.2) June 21, 2018 www.xilinx.com...
Page 234 27 cycles with C_AREA_OPTIMIZED • 29 cycles with C_AREA_OPTIMIZED • 23 cycles with C_AREA_OPTIMIZED Note This instruction is only available when the MicroBlaze parameter C_USE_FPU is set to 2 (Extended). MicroBlaze Processor Reference Guide Send Feedback UG984 (v2018.2) June 21, 2018 www.xilinx.com...
Page 235 The blocking versions (when ‘n’ bit is ‘0’) will stall MicroBlaze until the data from the interface is valid. The non-blocking versions will not stall MicroBlaze and will set carry to ‘0’ if the data was valid and to ‘1’ if the data was invalid. In case of an invalid access the destination register contents is undefined.
Page 236 • 2 cycles with C_AREA_OPTIMIZED The blocking versions of this instruction will stall the pipeline of MicroBlaze until the instruction can be completed. Interrupts are served when the parameter C_USE_EXTENDED_FSL_INSTR is set to 1, and the instruction is not atomic.
Page 237 The blocking versions (when ‘n’ bit is ‘0’) will stall MicroBlaze until the data from the interface is valid. The non-blocking versions will not stall MicroBlaze and will set carry to ‘0’ if the data was valid and to ‘1’ if the data was invalid. In case of an invalid access the destination register contents is undefined.
Page 238 • 2 cycles with C_AREA_OPTIMIZED The blocking versions of this instruction will stall the pipeline of MicroBlaze until the instruction can be completed. Interrupts are served unless the instruction is atomic, which ensures that the instruction cannot be interrupted. Notes The blocking versions of this instruction should not be placed in a delay slot, since this prevents interrupts from being served.
Page 239 1 cycle if (rA) = 0, otherwise 30 cycles with C_AREA_OPTIMIZED Note This instruction is only valid if MicroBlaze is configured to use a hardware divider (C_USE_DIV = 1). MicroBlaze Processor Reference Guide Send Feedback UG984 (v2018.2) June 21, 2018...
Page 240 16-bit immediate value field, a 32-bit immediate value cannot be used directly. However, 32-bit immediate values can be used in MicroBlaze. By default, Type B Instructions will take the 16-bit IMM field value and sign extend it to 32 bits to use as the immediate operand. This behavior can be overridden by preceding the Type B instruction with an imm instruction.
Page 241 Chapter 5: MicroBlaze Instruction Set Architecture Load Byte Unsigned rD, rA, rB lbur rD, rA, rB rD, rA, rB lbuea 1 1 0 0 0 0 0 R 0 EA 0 0 0 0 0 0 0 Description Loads a byte (8 bits) from the memory location that results from adding the contents of registers rA and rB.
Page 242 2 cycles with C_AREA_OPTIMIZED Notes The byte reversed instruction is only valid if MicroBlaze is configured to use reorder instructions (C_USE_REORDER_INSTR = 1). The extended address instruction is only valid if MicroBlaze is configured to use extended address (C_ADDR_SIZE > 32).
Page 243 Chapter 5: MicroBlaze Instruction Set Architecture lbui Load Byte Unsigned Immediate rD, rA, IMM lbui 1 1 1 0 0 0 Description Loads a byte (8 bits) from the memory location that results from adding the contents of register rA with the value in IMM, sign-extended to 32 bits.
Page 244 Chapter 5: MicroBlaze Instruction Set Architecture Load Halfword Unsigned rD, rA, rB lhur rD, rA, rB rD, rA, rB lhuea 1 1 0 0 0 1 0 R 0 EA 0 0 0 0 0 0 0 Description Loads a halfword (16 bits) from the halfword aligned memory location that results from adding the contents of registers rA and rB.
Page 245 2 cycles with C_AREA_OPTIMIZED Notes The halfword reversed instruction is only valid if MicroBlaze is configured to use reorder instructions (C_USE_REORDER_INSTR = 1). The extended address instruction is only valid if MicroBlaze is configured to use extended address (C_ADDR_SIZE > 32).
Page 246 Chapter 5: MicroBlaze Instruction Set Architecture lhui Load Halfword Unsigned Immediate rD, rA, IMM lhui 1 1 1 0 0 1 Description Loads a halfword (16 bits) from the halfword aligned memory location that results from adding the contents of register rA and the value in IMM, sign-extended to 32 bits. The data is placed in the least significant halfword of register rD and the most significant halfword in rD is cleared.
Page 247 Chapter 5: MicroBlaze Instruction Set Architecture Load Word rD, rA, rB rD, rA, rB rD, rA, rB lwea 1 1 0 0 1 0 0 R 0 EA 0 0 0 0 0 0 0 Description Loads a word (32 bits) from the word aligned memory location that results from adding the contents of registers rA and rB.
Page 248 2 cycles with C_AREA_OPTIMIZED Notes The word reversed instruction is only valid if MicroBlaze is configured to use reorder instructions (C_USE_REORDER_INSTR = 1). The extended address instruction is only valid if MicroBlaze is configured to use extended address (C_ADDR_SIZE > 32).
Page 249 Chapter 5: MicroBlaze Instruction Set Architecture Load Word Immediate rD, rA, IMM 1 1 1 0 1 0 Description Loads a word (32 bits) from the word aligned memory location that results from adding the contents of register rA and the value IMM, sign-extended to 32 bits. The data is placed in register rD. A data TLB miss exception occurs if virtual protected mode is enabled, and a valid translation entry corresponding to the address is not found in the TLB.A data storage exception occurs if access is...
Page 250 Chapter 5: MicroBlaze Instruction Set Architecture Load Word Exclusive rD, rA, rB 1 1 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 Description Loads a word (32 bits) from the word aligned memory location that results from adding the contents of registers rA and rB.
Page 251 Chapter 5: MicroBlaze Instruction Set Architecture Registers Altered • rD and MSR[C], unless an exception is generated, in which case they are unchanged • MSR[UM], MSR[VM], MSR[UMS], MSR[VMS], if a TLB miss exception or a data storage exception is generated •...
Page 252 Sleep Hibernate Suspend respectively to indicate this. The pipeline is halted, and MicroBlaze will not continue execution until a bit in the input signal is asserted. Wakeup Pseudocode if (IMM & 1) = 0 then wait for instruction side memory accesses if (IMM &...
Page 253 Chapter 5: MicroBlaze Instruction Set Architecture Move From Special Purpose Register rD, rS mfse rD, rS 1 0 0 1 0 1 0 E 0 0 0 1 0 Description Copies the contents of the special purpose register rS into register rD. The special purpose registers TLBLO and TLBHI are used to copy the contents of the Unified TLB entry indexed by TLBX.
Page 254 (dependent on pipeline stall behavior). An instruction that does not affect FSR must precede the MFS instruction to guarantee correct FSR value. EAR, ESR and BTR are only valid as operands when at least one of the MicroBlaze C_*_EXCEPTION parameters are set to 1.
Page 255 1 are cleared in the MSR. Bit positions that are 0 in the IMM value are left untouched. When MicroBlaze is configured to use an MMU (C_USE_MMU >= 1) this instruction is privileged for all IMM values except those only affecting C. This means that if the instruction is attempted in User Mode (MSR[UM] = 1) in this case a Privileged Instruction exception occurs.
Page 256 1 are set in the MSR. Bit positions that are 0 in the IMM value are left untouched. When MicroBlaze is configured to use an MMU (C_USE_MMU >= 1) this instruction is privileged for all IMM values except those only affecting C. This means that if the instruction is attempted in User Mode (MSR[UM] = 1) in this case a Privileged Instruction exception occurs.
Page 257 Physical Address Extension (PAE) is enabled. When MicroBlaze is configured to use an MMU (C_USE_MMU >= 1) this instruction is privileged. This means that if the instruction is attempted in User Mode (MSR[UM] = 1) a Privileged Instruction exception occurs.
Page 258 The PC, ESR, EAR, BTR, EDR and PVR0 - PVR12 cannot be written by the MTS instruction. The FSR is only valid as a destination if the MicroBlaze parameter C_USE_FPU is greater than 0. The SLR and SHR are only valid as a destination if the MicroBlaze parameter C_USE_STACK_PROTECTION is set to 1.
Page 259 3 cycles with C_AREA_OPTIMIZED Note This instruction is only valid if the target architecture has multiplier primitives, and if present, the MicroBlaze parameter C_USE_HW_MUL is greater than 0. MicroBlaze Processor Reference Guide Send Feedback UG984 (v2018.2) June 21, 2018 www.xilinx.com...
Page 260 MicroBlaze parameter C_USE_HW_MUL is set to 2 (Mul64). When MULH is used, bit 30 and 31 in the MUL instruction must be zero to distinguish between the two instructions. In previous versions of MicroBlaze, these bits were defined as zero, but the actual values were not relevant.
Page 261 MicroBlaze parameter C_USE_HW_MUL is set to 2 (Mul64). When MULHU is used, bit 30 and 31 in the MUL instruction must be zero to distinguish between the two instructions. In previous versions of MicroBlaze, these bits were defined as zero, but the actual values were not relevant.
Page 262 MicroBlaze parameter C_USE_HW_MUL is set to 2 (Mul64). When MULHSU is used, bit 30 and 31 in the MUL instruction must be zero to distinguish between the two instructions. In previous versions of MicroBlaze, these bits were defined as zero, but the actual values were not relevant.
Page 263 “imm” for details on using 32-bit immediate values. This instruction is only valid if the target architecture has multiplier primitives, and if present, the MicroBlaze parameter C_USE_HW_MUL is greater than 0. MicroBlaze Processor Reference Guide Send Feedback UG984 (v2018.2) June 21, 2018...
Page 264 Chapter 5: MicroBlaze Instruction Set Architecture Logical OR rD, rA, rB 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Description The contents of register rA are ORed with the contents of register rB; the result is placed into register Pseudocode ←...
Page 265 Chapter 5: MicroBlaze Instruction Set Architecture Logical OR with Immediate rD, rA, IMM 1 0 1 0 0 0 Description The contents of register rA are ORed with the extended IMM field, sign-extended to 32 bits; the result is placed into register rD.
Page 266 Chapter 5: MicroBlaze Instruction Set Architecture pcmpbf Pattern Compare Byte Find rD, rA, rB pcmpbf bytewise comparison returning position of first match 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 Description The contents of register rA is bytewise compared with the contents in register rB.
Page 267 Chapter 5: MicroBlaze Instruction Set Architecture pcmpeq Pattern Compare Equal rD, rA, rB pcmpeq equality comparison with a positive boolean result 1 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 Description The contents of register rA is compared with the contents in register rB.
Page 268 Chapter 5: MicroBlaze Instruction Set Architecture pcmpne Pattern Compare Not Equal rD, rA, rB pcmpne equality comparison with a negative boolean result 1 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 Description The contents of register rA is compared with the contents in register rB.
Page 269 FSLx Description MicroBlaze will write the value from register rA to the link x interface. If the available number of links set by C_FSL_LINKS is less than or equal to FSLx, link 0 is used. The put instruction has 16 variants.
Page 270 • 2 cycles with C_AREA_OPTIMIZED The blocking versions of this instruction will stall the pipeline of MicroBlaze until the instruction can be completed. Interrupts are served when the parameter is set to 1, and the instruction is not atomic. C_USE_EXTENDED_FSL_INSTR Notes To refer to an FSLx interface in assembly language, use rfsl0, rfsl1, ...
Page 271 The putd instruction has 16 variants. The blocking versions (when ‘n’ is ‘0’) will stall MicroBlaze until there is space available in the interface. The non-blocking versions will not stall MicroBlaze and will set carry to ‘0’ if space was available and to ‘1’...
Page 272 • 2 cycles with C_AREA_OPTIMIZED The blocking versions of this instruction will stall the pipeline of MicroBlaze until the instruction can be completed. Interrupts are served unless the instruction is atomic, which ensures that the instruction cannot be interrupted. Notes The blocking versions of this instruction should not be placed in a delay slot, since this prevents interrupts from being served.
Page 273 Chapter 5: MicroBlaze Instruction Set Architecture rsub Arithmetic Reverse Subtract rD, rA, rB rsub Subtract rsubc rD, rA, rB Subtract with Carry rD, rA, rB rsubk Subtract and Keep Carry rsubkc rD, rA, rB Subtract with Carry and Keep Carry...
Page 274 Chapter 5: MicroBlaze Instruction Set Architecture rsubi Arithmetic Reverse Subtract Immediate rD, rA, IMM rsubi Subtract Immediate rsubic rD, rA, IMM Subtract Immediate with Carry rD, rA, IMM rsubik Subtract Immediate and Keep Carry rsubikc rD, rA, IMM Subtract Immediate with Carry and Keep Carry...
Page 275 That delay slot instruction has breaks disabled. When MicroBlaze is configured to use an MMU (C_USE_MMU >= 1) this instruction is privileged. This means that if the instruction is attempted in User Mode (MSR[UM] = 1) a Privileged Instruction exception occurs.
Page 276 That delay slot instruction has interrupts disabled. When MicroBlaze is configured to use an MMU (C_USE_MMU >= 1) this instruction is privileged. This means that if the instruction is attempted in User Mode (MSR[UM] = 1) a Privileged Instruction exception occurs.
Page 277 This instruction always has a delay slot. The instruction following the RTED is always executed before the branch target. When MicroBlaze is configured to use an MMU (C_USE_MMU >= 1) this instruction is privileged. This means that if the instruction is attempted in User Mode (MSR[UM] = 1) a Privileged Instruction exception occurs.
Page 278 Chapter 5: MicroBlaze Instruction Set Architecture rtsd Return from Subroutine rA, IMM rtsd 1 0 1 1 0 1 1 0 0 0 0 Description Return from subroutine will branch to the location specified by the contents of rA plus the IMM field, sign-extended to 32 bits.
Page 279 Chapter 5: MicroBlaze Instruction Set Architecture Store Byte rD, rA, rB rD, rA, rB rD, rA, rB sbea 1 1 0 1 0 0 0 R 0 EA 0 0 0 0 0 0 0 Description Stores the contents of the least significant byte of register rD, into the memory location that results from adding the contents of registers rA and rB.
Page 280 2 cycles with C_AREA_OPTIMIZED Notes The byte reversed instruction is only valid if MicroBlaze is configured to use reorder instructions (C_USE_REORDER_INSTR = 1). The extended address instruction is only valid if MicroBlaze is configured to use extended address (C_ADDR_SIZE > 32).
Page 281 Chapter 5: MicroBlaze Instruction Set Architecture Store Byte Immediate rD, rA, IMM 1 1 1 1 0 0 Description Stores the contents of the least significant byte of register rD, into the memory location that results from adding the contents of register rA and the value IMM, sign-extended to 32 bits.
Page 282 Chapter 5: MicroBlaze Instruction Set Architecture sext16 Sign Extend Halfword rD, rA sext16 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 Description This instruction sign-extends a halfword (16 bits) into a word (32 bits). Bit 16 in rA will be copied into bits 0-15 of rD.
Page 283 Chapter 5: MicroBlaze Instruction Set Architecture sext8 Sign Extend Byte rD, rA sext8 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 Description This instruction sign-extends a byte (8 bits) into a word (32 bits). Bit 24 in rA will be copied into bits 0-23 of rD.
Page 284 Chapter 5: MicroBlaze Instruction Set Architecture Store Halfword rD, rA, rB rD, rA, rB rD, rA, rB shea 1 1 0 1 0 1 0 R 0 EA 0 0 0 0 0 0 0 Description Stores the contents of the least significant halfword of register rD, into the halfword aligned memory location that results from adding the contents of registers rA and rB.
Page 285 2 cycles with C_AREA_OPTIMIZED Notes The halfword reversed instruction is only valid if MicroBlaze is configured to use reorder instructions (C_USE_REORDER_INSTR = 1). The extended address instruction is only valid if MicroBlaze is configured to use extended address (C_ADDR_SIZE > 32).
Page 286 Chapter 5: MicroBlaze Instruction Set Architecture Store Halfword Immediate rD, rA, IMM 1 1 1 1 0 1 Description Stores the contents of the least significant halfword of register rD, into the halfword aligned memory location that results from adding the contents of register rA and the value IMM, sign-extended to 32 bits.
Page 287 Chapter 5: MicroBlaze Instruction Set Architecture Shift Right Arithmetic rD, rA 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Description Shifts arithmetically the contents of register rA, one bit to the right, and places the result in rD. The most significant bit of rA (that is, the sign bit) placed in the most significant bit of rD.
Page 288 Chapter 5: MicroBlaze Instruction Set Architecture Shift Right with Carry rD, rA 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 Description Shifts the contents of register rA, one bit to the right, and places the result in rD. The Carry flag is shifted in the shift chain and placed in the most significant bit of rD.
Page 289 Chapter 5: MicroBlaze Instruction Set Architecture Shift Right Logical rD, rA 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 Description Shifts logically the contents of register rA, one bit to the right, and places the result in rD. A zero is shifted in the shift chain and placed in the most significant bit of rD.
Page 290 Chapter 5: MicroBlaze Instruction Set Architecture Store Word rD, rA, rB rD, rA, rB rD, rA, rB swea 1 1 0 1 1 0 0 R 0 EA 0 0 0 0 0 0 0 Description Stores the contents of register rD, into the word aligned memory location that results from adding the contents of registers rA and rB.
Page 291 2 cycles with C_AREA_OPTIMIZED Notes The word reversed instruction is only valid if MicroBlaze is configured to use reorder instructions (C_USE_REORDER_INSTR = 1). The extended address instruction is only valid if MicroBlaze is configured to use extended address (C_ADDR_SIZE > 32).
Page 292 (rA)[16:23] ← (rD)[0:7] (rA)[24:31] Registers Altered • Latency • 1 cycle Note This instruction is only valid if MicroBlaze is configured to use reorder instructions (C_USE_REORDER_INSTR = 1). MicroBlaze Processor Reference Guide Send Feedback UG984 (v2018.2) June 21, 2018 www.xilinx.com...
Page 293 ← ( (rD)[16:31] rA)[0:15] Registers Altered • Latency • 1 cycle Note This instruction is only valid if MicroBlaze is configured to use reorder instructions (C_USE_REORDER_INSTR = 1). MicroBlaze Processor Reference Guide Send Feedback UG984 (v2018.2) June 21, 2018 www.xilinx.com...
Page 294 Chapter 5: MicroBlaze Instruction Set Architecture Store Word Immediate rD, rA, IMM 1 1 1 1 1 0 Description Stores the contents of register rD, into the word aligned memory location that results from adding the contents of registers rA and the value IMM, sign-extended to 32 bits.
Page 295 Chapter 5: MicroBlaze Instruction Set Architecture Store Word Exclusive rD, rA, rB 1 1 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 Description Conditionally stores the contents of register rD, into the word aligned memory location that results from adding the contents of registers rA and rB.
Page 296 Chapter 5: MicroBlaze Instruction Set Architecture Registers Altered • MSR[C], unless an exception is generated • MSR[UM], MSR[VM], MSR[UMS], MSR[VMS], if a TLB miss exception or a data storage exception is generated • ESR[EC], ESR[S], if an exception is generated •...
Page 297 The E bit is only taken into account when the parameter C_INTERCONNECT is set to 3 (ACE). When MicroBlaze is configured to use an MMU (C_USE_MMU >= 1) the instruction is privileged. This means that if the instruction is attempted in User Mode (MSR[UM] = 1) a Privileged Instruction exception occurs.
Page 298 Chapter 5: MicroBlaze Instruction Set Architecture Pseudocode if MSR[UM] = 1 then ← ESR[EC] 00111 else if C_DCACHE_USE_WRITEBACK = 1 then if T = 1 and EA = 1 then ← address (rA) & (rB) else ← address (rA) + (rB) else if E = 0 then ←...
Page 299 Chapter 5: MicroBlaze Instruction Set Architecture Notes The wdc, wdc.flush, wdc.clear and wdc.clear.ea instructions are independent of data cache enable (MSR[DCE]), and can be used either with the data cache enabled or disabled. The wdc.clear and wdc.clear.ea instructions are intended to invalidate a specific area in memory, for example a buffer to be written by a Direct Memory Access device.
Page 300 Register rA contains the address of the affected cache line. When MicroBlaze is configured to use an MMU (C_USE_MMU >= 1) this instruction is privileged. This means that if the instruction is attempted in User Mode (MSR[UM] = 1) a Privileged Instruction exception occurs.
Page 301 Chapter 5: MicroBlaze Instruction Set Architecture Logical Exclusive OR rD, rA, rB 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 Description The contents of register rA are XORed with the contents of register rB; the result is placed into register Pseudocode ←...
Page 302 Chapter 5: MicroBlaze Instruction Set Architecture xori Logical Exclusive OR with Immediate rD, rA, IMM xori 1 0 1 0 1 0 Description The IMM field is extended to 32 bits by concatenating 16 0-bits on the left. The contents of register rA are XOR’ed with the extended IMM field;...
Page 303 Chapter 5: MicroBlaze Instruction Set Architecture MicroBlaze Processor Reference Guide Send Feedback UG984 (v2018.2) June 21, 2018 www.xilinx.com...
Page 304: Appendix A: Performance And Resource Utilization
The details of the margin system characterization methodology is described “IP Characterization and fMAX Margin System Methodology” below. Maximum Frequencies The maximum frequencies for the MicroBlaze™ core are provided in Table A-1. The fastest speed grade of each family is used to generate the results in this table.
Page 305: Resource Utilization
Appendix A: Performance and Resource Utilization Resource Utilization The MicroBlaze core resource utilization for various parameter configurations are measured for the following devices: • Virtex-7 (Table A-2) • Kintex-7 (Table A-3) • Artix-7 (Table A-4) • Zynq-7000 (Table A-5) •...
Page 306 3731 Minimum Area Maximum Performance 4095 3195 Maximum Frequency 1102 Linux with MMU 3509 3111 Low-end Linux with MMU 3042 2493 Typical 2050 1672 Frequency Optimized 5855 5769 MicroBlaze Processor Reference Guide Send Feedback UG984 (v2018.2) June 21, 2018 www.xilinx.com...
Page 307 3737 Minimum Area Maximum Performance 4092 3195 Maximum Frequency 1101 Linux with MMU 3513 3112 Low-end Linux with MMU 3040 2496 Typical 2058 1672 Frequency Optimized 5828 5748 MicroBlaze Processor Reference Guide Send Feedback UG984 (v2018.2) June 21, 2018 www.xilinx.com...
Page 308 3741 Minimum Area Maximum Performance 4139 3196 Maximum Frequency 1099 Linux with MMU 3474 3131 Low-end Linux with MMU 3046 2497 Typical 2054 1676 Frequency Optimized 5947 5795 MicroBlaze Processor Reference Guide Send Feedback UG984 (v2018.2) June 21, 2018 www.xilinx.com...
Page 309 3741 Minimum Area Maximum Performance 4182 3195 Maximum Frequency 1117 Linux with MMU 3544 3119 Low-end Linux with MMU 3071 2493 Typical 2068 1672 Frequency Optimized 5947 5748 MicroBlaze Processor Reference Guide Send Feedback UG984 (v2018.2) June 21, 2018 www.xilinx.com...
Page 310 3743 Minimum Area Maximum Performance 4198 3195 Maximum Frequency 1100 Linux with MMU 3562 3124 Low-end Linux with MMU 3071 2493 Typical 2066 1673 Frequency Optimized 5965 5766 MicroBlaze Processor Reference Guide Send Feedback UG984 (v2018.2) June 21, 2018 www.xilinx.com...
Page 311 8192 8192 16384 C_DCACHE_BYTE_SIZE C_DCACHE_LINE_LEN C_DCACHE_USE_WRITEBACK C_DEBUG_ENABLED C_DIV_ZERO_EXCEPTION C_M_AXI_D_BUS_EXCEPTION C_FPU_EXCEPTION C_FSL_EXCEPTION C_FSL_LINKS C_ICACHE_LINE_LEN C_ILL_OPCODE_EXCEPTION C_M_AXI_I_BUS_EXCEPTION C_MMU_DTLB_SIZE C_MMU_ITLB_SIZE C_MMU_TLB_ACCESS C_MMU_ZONES C_NUMBER_OF_PC_BRK C_NUMBER_OF_RD_ADDR_BRK C_NUMBER_OF_WR_ADDR_BRK C_OPCODE_0x0_ILLEGAL C_PVR C_UNALIGNED_EXCEPTIONS C_USE_BARREL C_USE_DCACHE C_USE_DIV MicroBlaze Processor Reference Guide Send Feedback UG984 (v2018.2) June 21, 2018 www.xilinx.com...
Page 312: Ip Characterization And Fmax Margin System Methodology
) of IP operation within a system design. The method enables realistic performance reporting for any Xilinx FPGA architecture. The maximum frequency of a design is the maximum frequency at which the overall system can be implemented without encountering timing issues.
Page 313 Tool Options and Other Factors Xilinx tools offer a number of options and settings that provide a trade-off between design performance, resource usage, implementation run time, and memory footprint. The settings that produce the best results for one design might not necessarily work for another design.
Page 314: Appendix B: Additional Resources And Legal Notices
Documentation Navigator and Design Hubs Xilinx® Documentation Navigator provides access to Xilinx documents, videos, and support resources, which you can filter and search to find information. To open the Xilinx Documentation Navigator (DocNav): • From the Vivado® IDE, select Help > Documentation and Tutorials.
Page 315: References
2. LogiCore IP Soft Error Mitigation Controller Product Guide (PG036) 3. LogiCore IP Processor LMB BRAM Interface Controller Product Guide (PG112) 4. MicroBlaze Debug Module (MDM) Product Guide (PG115) 5. Device Reliability Report User Guide (UG116) 6. LogiCore IP System Cache Product Guide (PG118) 7.
Page 316: Training Resources
Xilinx’s Terms of Sale which can be viewed at https://www.xilinx.com/legal.htm#tos; IP cores may be subject to warranty and support terms contained in a license issued to you by Xilinx. Xilinx products are not designed or intended to be fail-safe or for use in any application requiring fail-safe performance;...

Xilinx MicroBlaze Reference Manual

Chapter 1: Introduction

Chapter 2: Microblaze Architecture

Chapter 3: Microblaze Signal Interface Description

Chapter 4 : Microblaze Application Binary Interface

Chapter 5: Microblaze Instruction Set Architecture

Appendix A: Performance and Resource Utilization

Appendix B: Additional Resources and Legal Notices

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