Xilinx MicroBlaze Reference Manual page 74

• For all other exceptions the register R17 is loaded with the program counter value of
the subsequent instruction, unless the exception is caused by an instruction in a branch
delay slot. If the exception is caused by an instruction in a branch delay slot, the
ESR[DS] bit is set. In this case the exception handler should resume execution from the
branch target address stored in BTR.
The EE and EIP bits in MSR are automatically reverted when executing the
The VM and UM bits in MSR are automatically reverted from VMS and UMS when executing
the ,
RTED RTBD
Exception Priority
When two or more exceptions occur simultaneously, they are handled in the following
order, from the highest priority to the lowest:
• Instruction Bus Exception
• Instruction TLB Miss Exception
• Instruction Storage Exception
• Illegal Opcode Exception
• Privileged Instruction Exception or Stack Protection Violation Exception
• Data TLB Miss Exception
• Data Storage Exception
• Unaligned Exception
• Data Bus Exception
• Divide Exception
• FPU Exception
• Stream Exception
Exception Causes
• Stream Exception: The AXI4-Stream exception is caused by executing a
instruction with the 'e' bit set to '1' when there is a control bit mismatch.
• Instruction Bus Exception: The instruction bus exception is caused by errors when
reading data from memory.
The instruction peripheral AXI4 interface (
-
response on
The instruction cache AXI4 interface (
-
M_AXI_IC_RRESP
MicroBlaze Processor Reference Guide
UG984 (v2018.2) June 21, 2018
, and instructions.
RTID
M_AXI_IP_RRESP
. The exception can only occur when
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Chapter 2: MicroBlaze Architecture
) exception is caused by an error
M_AXI_IP
.
) is caused by an error response on
M_AXI_IC
instruction.
RTED
or
get
C_ICACHE_ALWAYS_USED
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getd
is set
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