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Xilinx LogiCORE IP MAC v8.5 User Manual

Ug144 1-gigabit ethernet
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-- DISCONTINUED PRODUCT --
LogiCORE™ IP
1-Gigabit Ethernet
MAC v8.5
User Guide
UG144 April 24, 2009
R

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Summary of Contents for Xilinx LogiCORE IP MAC v8.5

  • Page 1 -- DISCONTINUED PRODUCT -- LogiCORE™ IP 1-Gigabit Ethernet MAC v8.5 User Guide UG144 April 24, 2009...
  • Page 2 -- DISCONTINUED PRODUCT -- Xilinx is providing this product documentation, hereinafter “Information,” to you “AS IS” with no warranty of any kind, express or implied. Xilinx makes no representation that the Information, or any particular implementation thereof, is free from any claims of infringement. You are responsible for obtaining any rights you may require for any implementation based on the Information.

  • Page 3: Revision History

    Version Revision 09/30/04 Initial Xilinx release. 04/28/05 Updated to 1-Gigabit Ethernet MAC version 6.0, Xilinx tools v7.1i SP1. 01/18/06 Updated to 1-Gigabit Ethernet MAC version 7.0, Xilinx tools v8.1i. 07/13/06 Updated to 1-Gigabit Ethernet MAC version 8.0, Xilinx tools v8.2i.
  • Page 4 -- DISCONTINUED PRODUCT -- www.xilinx.com 1-Gigabit Ethernet MAC v8.5 User Guide UG144 April 24, 2009...

  • Page 5: Table Of Contents

    ..........19 Related Xilinx Ethernet Products and Services .
  • Page 6 ........... 76 www.xilinx.com 1-Gigabit Ethernet MAC v8.5 User Guide...
  • Page 7 ........... . . 119 Connecting the Ethernet Statistics Core to Provide Statistics Gathering ..119 1-Gigabit Ethernet MAC v8.5 User Guide www.xilinx.com UG144 April 24, 2009...
  • Page 8 Generating the Xilinx Netlist ........

  • Page 9: Schedule Of Figures

    Figure 6-3: Pause Request Timing..........56 Figure 6-4: Flow Control Implementation Triggered from FIFO Occupancy..59 1-Gigabit Ethernet MAC v8.5 User Guide www.xilinx.com UG144 April 24, 2009...
  • Page 10 Figure 10-5: Reset Circuit for a Single Clock/reset Domain......112 www.xilinx.com 1-Gigabit Ethernet MAC v8.5 User Guide...
  • Page 11 Figure A-3: Frame Transfer with Flow Control ........130 Appendix B: Core Verification, Compliance, and Interoperability Appendix C: Calculating DCM Phase-Shifting Appendix D: Core Latency 1-Gigabit Ethernet MAC v8.5 User Guide www.xilinx.com UG144 April 24, 2009...
  • Page 12 -- DISCONTINUED PRODUCT -- www.xilinx.com 1-Gigabit Ethernet MAC v8.5 User Guide UG144 April 24, 2009...

  • Page 13: Schedule Of Tables

    Table 8-7: Management Configuration Word ........82 1-Gigabit Ethernet MAC v8.5 User Guide www.xilinx.com UG144 April 24, 2009...
  • Page 14 Table A-4: Receive FIFO LocalLink Interface ........129 Appendix B: Core Verification, Compliance, and Interoperability Appendix C: Calculating DCM Phase-Shifting Appendix D: Core Latency www.xilinx.com 1-Gigabit Ethernet MAC v8.5 User Guide UG144 April 24, 2009...

  • Page 15: Preface: About This Guide

    The LogiCORE™ IP 1-Gigabit Ethernet MAC User Guide provides information about generating the core, customizing and simulating the core utilizing the provided example design, and running the design files through implementation using the Xilinx tools. Guide Contents This guide contains the following chapters: •...

  • Page 16: Conventions

    A read of address The prefix ‘0x’ or the suffix ‘h’ 0x00112975 returned indicate hexadecimal notation 45524943h. Notations An ‘_n’ means the signal is usr_teof_n is active low. active low www.xilinx.com 1-Gigabit Ethernet MAC v8.5 User Guide UG144 April 24, 2009...

  • Page 17: Online Document

    “Title Formats” in document Chapter 1 for details. Go to www.xilinx.com for the Blue, underlined text Hyperlink to a website (URL) latest speed files. List of Acronyms The following table describes acronyms used in this manual.
  • Page 18 Reduced Gigabit Media Independent Interface SGMII Serial Gigabit Media Independent Interface VHDL VHSIC Hardware Description Language (VHSIC an acronym for Very High-Speed Integrated Circuits). Verilog Compiled Simulator VLAN Virtual LAN (Local Area Network) www.xilinx.com 1-Gigabit Ethernet MAC v8.5 User Guide UG144 April 24, 2009...

  • Page 19: Chapter 1: Introduction

    Xilinx. About the Core The GEMAC core is a Xilinx CORE Generator™ IP core, included in the latest IP Update on the Xilinx IP Center. For detailed information about the core, see the GEMAC product page.

  • Page 20: Specifications

    For technical support, see support.xilinx.com/. Questions are routed to a team of engineers with expertise using the GEMAC core. Xilinx will provide technical support for use of this product as described in the 1-Gigabit Ethernet MAC User Guide and the 1-Gigabit Ethernet MAC Getting Started Guide. Xilinx cannot guarantee timing, functionality, or support of this product for designs that do not follow these guidelines.

  • Page 21: Chapter 2: Core Architecture

    Client Transmit Engine Transmitter Interface Flow Control To Physical Sublayers Client Receive Engine Receiver Interface Optional Address Filter Optional Management Client Configuration MDIO Management Interface Figure 2-1: Block Diagram 1-Gigabit Ethernet MAC v8.5 User Guide www.xilinx.com UG144 April 24, 2009...

  • Page 22: Core Components

    GMII Block This implements GMII style signaling for the physical interface of the core and is typically attached to a physical layer device (PHY), either off-chip or internally integrated. www.xilinx.com 1-Gigabit Ethernet MAC v8.5 User Guide UG144 April 24, 2009...

  • Page 23: Core Interfaces

    Figure 2-2: Component Pinout for MAC with Optional Management Interface 1-Gigabit Ethernet MAC v8.5 User Guide www.xilinx.com UG144 April 24, 2009...

  • Page 24: Gmac Core Without Management Interface And With Address Filter

    Figure 2-3: Component Pinout for MAC without Optional Management Interface and with Optional Address Filter www.xilinx.com 1-Gigabit Ethernet MAC v8.5 User Guide UG144 April 24, 2009...

  • Page 25: Gemac Core Without Management Interface And Without Address Filter

    Figure 2-4: Component Pinout for MAC without Optional Management Interface or Optional Address Filter 1-Gigabit Ethernet MAC v8.5 User Guide www.xilinx.com UG144 April 24, 2009...

  • Page 26: Client Side Interface

    Output gtx_clk Provides statistical information about the last frame transmitted. tx_statistics_valid Output gtx_clk Asserted at end of frame transmission, indicating that the tx_statistics_vector is valid. www.xilinx.com 1-Gigabit Ethernet MAC v8.5 User Guide UG144 April 24, 2009...
  • Page 27 Direction Clock Domain Description pause_req Input gtx_clk Pause request. sends a pause frame down the link. pause_val[15:0] Input gtx_clk Pause value; inserted into the parameter field of the transmitted pause frame. 1-Gigabit Ethernet MAC v8.5 User Guide www.xilinx.com UG144 April 24, 2009...
  • Page 28 Used to assess the MAC unicast address registers when the Management Interface is not used Note: All bits are registered on input but may be treated as asynchronous inputs. www.xilinx.com 1-Gigabit Ethernet MAC v8.5 User Guide UG144 April 24, 2009...

  • Page 29: Physical Side Interface

    Receive clock from external PHY (125 MHz) gmii_rxd[7:0] Input gmii_rx_clk Received data to MAC gmii_rx_dv Input gmii_rx_clk Received control signal to MAC gmii_rx_er Input gmii_rx_clk Received control signal to MAC 1-Gigabit Ethernet MAC v8.5 User Guide www.xilinx.com UG144 April 24, 2009...

  • Page 30: Mdio Interface

    MDIO bus. 1. mdio_in, mdio_out can be connected to a Tri-state buffer to create a bi-directional mdio_tri mdio signal suitable for connection to an external PHY. www.xilinx.com 1-Gigabit Ethernet MAC v8.5 User Guide UG144 April 24, 2009...

  • Page 31: Chapter 3: Generating The Core

    -- DISCONTINUED PRODUCT -- Chapter 3 Generating the Core The GEMAC core is generated through the Xilinx CORE Generator™ using a graphical user interface (GUI). This chapter describes the GUI options used to generate and customize the core. Graphical User Interface Figure 3-1 shows the main GEMAC core user GUI screen.

  • Page 32: Component Name

    This option is only available when the Management Interface and Address Filter have been selected. The default is to use 4 address table entries. Physical Interface Depending on the target Xilinx FPGA architecture, it may be possible to select from two different physical interface choices for the core: •...

  • Page 33: Output Generation

    Mentor Graphics ModelSim, Cadence IUS or Synopsys VCS simulators. See the 1-Gigabit Ethernet MAC Getting Started Guide for more information about the CORE Generator output files and for details on the HDL example design. 1-Gigabit Ethernet MAC v8.5 User Guide www.xilinx.com UG144 April 24, 2009...
  • Page 34 -- DISCONTINUED PRODUCT -- Chapter 3: Generating the Core www.xilinx.com 1-Gigabit Ethernet MAC v8.5 User Guide UG144 April 24, 2009...

  • Page 35: Chapter 4: Designing With The Core

    The following sections discuss the design steps required for various implementations. For best results, carefully follow the logic design guidelines. Design Steps Generate the core from the Xilinx CORE Generator™. See Chapter 3, “Generating the Core.” Using the Example Design as a Starting Point...

  • Page 36: Figure 4-1: 1-Gigabit Ethernet Mac Core Example Design

    Run the implement script in the /implement directory to create a top-level netlist for the design. The script may also run the Xilinx tools map, par, and bitgen, creating a bitstream that can be downloaded to a Xilinx device. SimPrim-based simulation models for the entire design are also produced by the implement scripts.

  • Page 37: Know The Degree Of Difficulty

    NGC netlist (which appears as a black box to synthesis tools). Run the Xilinx tools map, par, and bitgen to create a bitstream that can be downloaded to a Xilinx device. Care must be taken to constrain the design correctly, and the UCF produced by the CORE Generator should be used as the basis for the your own UCF.

  • Page 38: Keep It Registered

    While registering signals may not be possible for all paths, it simplifies timing analysis and makes it easier for the Xilinx tools to place-and-route the design. Recognize Timing Critical Signals The UCF provided with the example design identifies the critical signals and timing constraints that should be applied.

  • Page 39: Chapter 5: Using The Client Side Data Path

    The MAC asserts the rx_good_frame signal to indicate that the frame was successfully received and that the frame should be analyzed by the client. 1-Gigabit Ethernet MAC v8.5 User Guide www.xilinx.com UG144 April 24, 2009...

  • Page 40: Rx_Good_Frame, Rx_Bad_Frame Timing

    This is after the FCS field has been received (and after reception of carrier extension, if present). Therefore, either rx_good_frame or rx_bad_frame is asserted following frame reception at the beginning of the interframe gap. www.xilinx.com 1-Gigabit Ethernet MAC v8.5 User Guide UG144 April 24, 2009...

  • Page 41: Frame Reception With Errors

    A valid pause frame, addressed to the MAC, is received when flow control is enabled. Please see “Overview of Flow Control,” on page gmii_rx_clk rx_data[7:0] DATA rx_data_valid rx_good_frame rx_bad_frame Figure 5-2: Frame Reception with Error 1-Gigabit Ethernet MAC v8.5 User Guide www.xilinx.com UG144 April 24, 2009...

  • Page 42: Client-Supplied Fcs Passing

    Tag Control Information bytes, V1 and V2. More information on the interpretation of these bytes may be found in IEEE 802.3-2005 standard. gmii_rx_clk rx_data[7:0] 81 00V1V2 VLAN DATA rx_data_valid rx_good_frame rx_bad_frame Figure 5-4: Reception of a VLAN Tagged Frame www.xilinx.com 1-Gigabit Ethernet MAC v8.5 User Guide UG144 April 24, 2009...

  • Page 43: Maximum Permitted Frame Length

    Instead, rx_data_valid is deasserted before the start of the FCS field, and any padding is not removed from the frame. 1-Gigabit Ethernet MAC v8.5 User Guide www.xilinx.com UG144 April 24, 2009...

  • Page 44: Address Filter

    Ethernet MAC core. They are not backwards compatible with previous versions of the 1-Gigabit Ethernet MAC core (see Table 5-3 for Receiver Statistic Vector conversion details) gmii_rx_clk rx_statistics_valid rx_statistics_vector[27:0] Figure 5-5: Receiver Statistics Vector Timing www.xilinx.com 1-Gigabit Ethernet MAC v8.5 User Guide UG144 April 24, 2009...
  • Page 45 Do not use this as an enable signal to indicate that data is present on rx_data. VLAN frame Asserted if the previous frame contained a VLAN identifier in the length/type field when receiver VLAN operation is enabled. 1-Gigabit Ethernet MAC v8.5 User Guide www.xilinx.com UG144 April 24, 2009...
  • Page 46 Bit 26 (reserved) has been inserted into version 8.5 for statistic vector compatibility with the Tri- Mode Ethernet MAC LogiCORE™. 25:0 25:0 No differences www.xilinx.com 1-Gigabit Ethernet MAC v8.5 User Guide UG144 April 24, 2009...

  • Page 47: Transmitting Outbound Frames

    GEMAC core is configured for client-passed FCS; in this case, the client must also supply the padding to maintain the minimum frame length. See “Client- Supplied FCS Passing” for more information. 1-Gigabit Ethernet MAC v8.5 User Guide www.xilinx.com UG144 April 24, 2009...

  • Page 48: Client-Supplied Fcs Passing

    When an underrun occurs, tx_data_valid may be asserted on the clock cycle after the tx_underrun assertion to request a new transmission. gtx_clk tx_data[7:0] DATA tx_data_valid tx_ack tx_underrun Figure 5-8: Frame Transmission with Underrun www.xilinx.com 1-Gigabit Ethernet MAC v8.5 User Guide UG144 April 24, 2009...

  • Page 49: Vlan Tagged Frames

    Statistics core is used with the MAC, then accuracy cannot be guaranteed if the interframe gap adjustment is set to less than 12 idles. However, the tx_statistic_vector and rx_statistic_vector values will always remain correct. 1-Gigabit Ethernet MAC v8.5 User Guide www.xilinx.com UG144 April 24, 2009...

  • Page 50: Transmitter Statistics Vector

    Ethernet MAC core. They are not backwards compatible with previous versions of the 1-Gigabit Ethernet MAC core (see Table 5-5 for Transmitter Statistic Vector conversion details). gtx_clk tx_statistic_valid tx_statistic_vector[31:0] Figure 5-11: Transmitter Statistic Vector Timing www.xilinx.com 1-Gigabit Ethernet MAC v8.5 User Guide UG144 April 24, 2009...
  • Page 51 Broadcast Frame Asserted if the previous frame contained a broadcast address in the destination address field. Successful Frame Asserted if the previous frame was transmitted without error. 1-Gigabit Ethernet MAC v8.5 User Guide www.xilinx.com UG144 April 24, 2009...
  • Page 52 Bit 30 is equivalent to bit 20 of all previous core versions. 29:20 Reserved: have been inserted into version 8.5 for statistic vector compatibility with the Tri- Mode Ethernet MAC LogiCORE. 19:0 19:0 No differences www.xilinx.com 1-Gigabit Ethernet MAC v8.5 User Guide UG144 April 24, 2009...

  • Page 53: Chapter 6: Using Flow Control

    Flow Control Requirement Figure 6-1 illustrates the requirements for Flow Control. User System Client Logic User MAC Link Partner MAC 125MHz -100ppm FIFO 125MHz +100ppm Figure 6-1: Requirement for Flow Control 1-Gigabit Ethernet MAC v8.5 User Guide www.xilinx.com UG144 April 24, 2009...

  • Page 54: Flow Control Basics

    FIFO experienced an overflow condition. This provides time for the FIFO to be emptied to a safe level before normal operation resumes, thus safeguarding the system against FIFO overflow conditions and frame loss. www.xilinx.com 1-Gigabit Ethernet MAC v8.5 User Guide UG144 April 24, 2009...

  • Page 55: Pause Control Frames

    This defines the number of pause_quantum (512 bit times of the particular implementation). For 1-Gigabit Ethernet, a single pause_quantum corresponds to 512 ns. 1-Gigabit Ethernet MAC v8.5 User Guide www.xilinx.com UG144 April 24, 2009...

  • Page 56: Flow Control Operation Of The Gemac

    81). Any type of control frame can be transmitted through the core through the client interface using the same transmission procedure as a standard Ethernet frame (see “Transmitting Outbound Frames,” on page 47). www.xilinx.com 1-Gigabit Ethernet MAC v8.5 User Guide UG144 April 24, 2009...

  • Page 57: Receiving A Pause Control Frame

    The frame is passed to the client for interpretation. It is then the responsibility of the client to drop this control frame and to act on it by ceasing transmission through the core, if applicable. 1-Gigabit Ethernet MAC v8.5 User Guide www.xilinx.com UG144 April 24, 2009...

  • Page 58: Flow Control Implementation Example

    MAC immediately resumes transmission (it does not wait for the original requested pause duration to expire). This pause control frame can therefore be considered a “pause cancel” command. www.xilinx.com 1-Gigabit Ethernet MAC v8.5 User Guide UG144 April 24, 2009...

  • Page 59: Figure 6-4: Flow Control Implementation Triggered From Fifo Occupancy

    On receiving this second pause control frame, the link partner MAC resumes transmission. Normal operation resumes and the FIFO occupancy again gradually increases over time. At point C, this Flow Control cycle repeats. 1-Gigabit Ethernet MAC v8.5 User Guide www.xilinx.com UG144 April 24, 2009...
  • Page 60 -- DISCONTINUED PRODUCT -- Chapter 6: Using Flow Control www.xilinx.com 1-Gigabit Ethernet MAC v8.5 User Guide UG144 April 24, 2009...

  • Page 61: Chapter 7: Using The Physical Side Interface

    1-Gigabit Ethernet MAC v8.5 User Guide www.xilinx.com UG144 April 24, 2009...

  • Page 62: Figure 7-1: External Gmii Transmitter Logic

    1-Gigabit Ethernet MAC LogiCORE OBUF gmii_txd[0] gmii_txd_reg[0] gmii_txd_int[0] gtx_clk gmii_txd[0] OPAD OBUF gmii_tx_en gmii_tx_en_int gmii_tx_en_reg gmii_tx_en OPAD OBUF gmii_tx_er gmii_tx_er_int gmii_tx_er_reg gmii_tx_er OPAD Figure 7-1: External GMII Transmitter Logic www.xilinx.com 1-Gigabit Ethernet MAC v8.5 User Guide UG144 April 24, 2009...

  • Page 63: Gmii Receiver Logic

    IOB LOGIC IBUF gmii_rxd[0] gmii_rxd_reg[0] gmii_rxd[0] IPAD IBUF gmii_rx_dv gmii_rx_dv_reg gmii_rx_dv IPAD IBUF gmii_rx_er gmii_rx_er_reg gmii_rx_er IPAD Figure 7-2: External GMII Receiver Logic for Spartan-3, Spartan-3E, and Spartan-3A Devices 1-Gigabit Ethernet MAC v8.5 User Guide www.xilinx.com UG144 April 24, 2009...
  • Page 64 DCM reset signal must be connected correctly: • This can be achieved by connecting the reset_200ms signal to the reset_200ms_in signal at any level of example design HDL hierarchy. www.xilinx.com 1-Gigabit Ethernet MAC v8.5 User Guide UG144 April 24, 2009...

  • Page 65: Figure 7-3: External Gmii Receiver Logic For Virtex-5 Devices

    1-Gigabit Ethernet MAC LogiCORE gmii_rx_clk IBUF gmii_rxd[0] gmii_rxd_reg[0] IODELAY gmii_rxd[0] IPAD IBUF gmii_rx_dv gmii_rx_dv_reg IODELAY gmii_rx_dv IPAD IBUF gmii_rx_er gmii_rx_er_reg IODELAY gmii_rx_er IPAD Figure 7-3: External GMII Receiver Logic for Virtex-5 Devices 1-Gigabit Ethernet MAC v8.5 User Guide www.xilinx.com UG144 April 24, 2009...

  • Page 66: Implementing External Rgmii

    IOB LOGIC FDDRRSE 1-Gigabit Ethernet MAC Core gmii_txd_int[0] gtx_clk gmii_txd[0] OBUF rgmii_txd[0] OPAD gmii_txd_int[4] gmii_txd[4] FDDRRSE gmii_tx_en_int gmii_tx_en OBUF rgmii_tx_ctl OPAD gmii_tx_er_int gmii_tx_er Figure 7-4: External RGMII Transmitter Logic www.xilinx.com 1-Gigabit Ethernet MAC v8.5 User Guide UG144 April 24, 2009...
  • Page 67 IOBs in ODDR components. These components convert the input signals into one double-data-rate signal. These signals are then output through OBUFs before being driven to output pads. 1-Gigabit Ethernet MAC v8.5 User Guide www.xilinx.com UG144 April 24, 2009...

  • Page 68: Figure 7-5: External Rgmii Transmitter Logic In Virtex-4 Devices

    (when the DCM is held in reset, the DCM input clock is instead selected). This is required to always provided a reliable clock for the receiver logic DCM: see “DCM Reset circuitry”. www.xilinx.com 1-Gigabit Ethernet MAC v8.5 User Guide UG144 April 24, 2009...

  • Page 69: Figure 7-6: External Rgmii Transmitter Logic In Virtex-5 Devices

    OBUF rgmii_txd[0] gmii_txd_int[4] gmii_txd[4] gtx_clk IODELAY OPAD IOB LOGIC ODDR gmii_tx_en_int OBUF gmii_tx_en rgmii_tx_ctl gmii_tx_er_int gmii_tx_er OPAD IODELAY Figure 7-6: External RGMII Transmitter Logic in Virtex-5 Devices 1-Gigabit Ethernet MAC v8.5 User Guide www.xilinx.com UG144 April 24, 2009...

  • Page 70: Rgmii Receiver Logic

    For Spartan-3 families, the reset pulse is transferred into the DCM input clock (rgmii_rxc from Figure 7-7). Here it is extended to three DCM clock periods duration and routed to the reset input of the DCM. www.xilinx.com 1-Gigabit Ethernet MAC v8.5 User Guide UG144 April 24, 2009...

  • Page 71: Figure 7-7: External Rgmii Receiver Logic

    IOB LOGIC IBUF rgmii_rxd_ddr[0] rgmii_rxd_reg[0] rgmii_rxd[0] gmii_rxd_reg[0] gmii_rxd[0] IPAD rgmii_rxd_reg[4] rgmii_rxd_ddr[4] gmii_rxd_reg[4] gmii_rxd[4] IBUF rgmii_rx_dv_reg rgmii_rx_dv_ddr rgmii_rx_ctl gmii_rx_dv_reg gmii_rx_dv IPAD rgmii_rx_ctl_ddr rgmii_rx_ctl_reg gmii_rx_er_reg gmii_rx_er Figure 7-7: External RGMII Receiver Logic 1-Gigabit Ethernet MAC v8.5 User Guide www.xilinx.com UG144 April 24, 2009...
  • Page 72 However, to re-iterate, when implementing the design in real hardware, the DCM reset signal must be connected correctly: www.xilinx.com 1-Gigabit Ethernet MAC v8.5 User Guide UG144 April 24, 2009...

  • Page 73: Figure 7-8: External Rgmii Receiver Logic For Virtex-4 Devices

    IOB LOGIC IDDR gmii_rxd_int[0] IBUF gmii_rxd[0] rgmii_rxd[0] gmii_rxd_int[4] gmii_rxd[4] IPAD IOB LOGIC IDDR gmii_rx_dv_int IBUF gmii_rx_dv rgmii_rx_ctl gmii_rx_er_int gmii_rx_er IPAD Figure 7-8: External RGMII Receiver Logic for Virtex-4 Devices 1-Gigabit Ethernet MAC v8.5 User Guide www.xilinx.com UG144 April 24, 2009...

  • Page 74: Figure 7-9: External Rgmii Receiver Logic For Virtex-5 Devices

    IDELAY_VALUE determines the tap delay value. An IDELAYCTRL primitive must be instantiated for this mode of operation. See the Virtex-5 User Guide for more information on the use of IDELAYCTRL and IODELAY components. www.xilinx.com 1-Gigabit Ethernet MAC v8.5 User Guide UG144 April 24, 2009...

  • Page 75: Rgmii Inband Status Decoding Logic

    OPAD OBUF inband_duplex_status OPAD gmii_rx_clk_bufg gmii_rx_clk RGMII RECEIVER LOGIC gmii_rxd_reg[0] gmii_rxd[0] gmii_rxd_reg[1] gmii_rxd[1] gmii_rxd_reg[2] gmii_rxd[2] gmii_rxd_reg[3] gmii_rxd[3] gmii_rx_dv_reg gmii_rx_dv gmii_rx_er_reg gmii_rx_er Figure 7-10: RGMII Inband Status Decoding Logic 1-Gigabit Ethernet MAC v8.5 User Guide www.xilinx.com UG144 April 24, 2009...

  • Page 76: Using The Mdio Interface

    Connecting the MDIO to an Internally Integrated PHY The MDIO ports of the GEMAC core can be connected to the MDIO ports of an internally integrated physical-layer device, such as the MDIO port of the Xilinx Ethernet 1000BASE- X PCS/PMA or SGMII core. See Chapter 11, “Interfacing to Other Cores”...

  • Page 77: Using The Optional Management Interface

    ≥ 10 MHz Configuring the GEMAC core to derive the mdc signal from this clock is detailed in “MDIO Interface,” on page 1-Gigabit Ethernet MAC v8.5 User Guide www.xilinx.com UG144 April 24, 2009...

  • Page 78: Configuration Registers

    Address Table Configuration (Word 0) (if Address Filter is present) 0x38C-0x38F Address Table Configuration (Word 1) (if Address Filter is present) 0x390-0x393 Address Filter Mode (if Address Filter is present) www.xilinx.com 1-Gigabit Ethernet MAC v8.5 User Guide UG144 April 24, 2009...
  • Page 79 Receiver Enable. If set to ‘1,’ the receiver block will be operational. If set to ‘0,’ the block will ignore activity on the physical interface RX port. 1-Gigabit Ethernet MAC v8.5 User Guide www.xilinx.com UG144 April 24, 2009...

  • Page 80: Chapter 8: Configuration And Status

    VLAN Enable When this bit is set to ‘1,’ the transmitter will allow the transmission of VLAN tagged frames. Transmit Enable When this bit is ‘1,’ the transmitter is operational. When it is ‘0,’ the transmitter is disabled. www.xilinx.com 1-Gigabit Ethernet MAC v8.5 User Guide UG144 April 24, 2009...
  • Page 81 Flow Control Enable (TX) When this bit is ‘1,’ asserting the PAUSE_REQ signal will send a flow control frame out from the transmitter. When this bit is ‘0,’ asserting the PAUSE_REQ signal has no effect. Reserved 1-Gigabit Ethernet MAC v8.5 User Guide www.xilinx.com UG144 April 24, 2009...

  • Page 82: Chapter 8: Configuration And Status

    AA-BB-CC-DD-EE-FF would be stored in Address[47:0] as 0xFFEEDDCCBBAA. Table 8-9: Unicast Address Word 1 Default Bits Description Value 15-0 All 0s Address filter unicast address[47:32]. 31-16 Reserved www.xilinx.com 1-Gigabit Ethernet MAC v8.5 User Guide UG144 April 24, 2009...
  • Page 83 8-1. When accessing the configuration registers (when host_addr[9] = ‘1’ and host_miim_sel = ‘0’), the upper bit of host_opcode functions as an active low write enable signal. The lower host_opcode bit is a don’t care bit. 1-Gigabit Ethernet MAC v8.5 User Guide www.xilinx.com UG144 April 24, 2009...

  • Page 84: Figure 8-1: Configuration Register Write Timing

    8-2. In this case, the contents of the register appear on host_rd_data the host_clk edge after the register address is asserted onto host_addr. host_clk host_miim_sel host_opcode[1] host_addr[8:0] host_addr[9] host_rd_data[31:0] Figure 8-2: Configuration Register Read Timing www.xilinx.com 1-Gigabit Ethernet MAC v8.5 User Guide UG144 April 24, 2009...

  • Page 85: Figure 8-3: Address Table Write Timing

    On the next cycle the least significant word appears on the hostrddata bus. One cycle afterwards, the most significant 16-bits are output on the lower 16 bits of the bus. 1-Gigabit Ethernet MAC v8.5 User Guide www.xilinx.com UG144 April 24, 2009...

  • Page 86: Mdio Interface

    All transactions are initiated by the STA entity. The GEMAC core implements a STA and can be connected to MMDs (PHY devices) to access their management registers. www.xilinx.com 1-Gigabit Ethernet MAC v8.5 User Guide UG144 April 24, 2009...

  • Page 87: Figure 8-5: Typical Mdio-Managed System

    0 1 P4 P3 P2 P1 P0 R4 R3 R2 R1 R0 1 0 D15 IDLE 32 bits PHYAD REGAD 16-bit WRITE DATA IDLE Figure 8-6: MDIO Write Transaction 1-Gigabit Ethernet MAC v8.5 User Guide www.xilinx.com UG144 April 24, 2009...

  • Page 88: Figure 8-7: Mdio Read Transaction

    MDIO interface. For details of the register map of PHY layer devices and a detailed description of the operation of the MDIO interface itself, see IEEE 802.3-2005. www.xilinx.com 1-Gigabit Ethernet MAC v8.5 User Guide UG144 April 24, 2009...

  • Page 89: Figure 8-8: Mdio Access Through Management Interface

    GEMAC core; if the transaction is a read, the data is available on the host_rd_data[15:0] bus at this time. 1-Gigabit Ethernet MAC v8.5 User Guide www.xilinx.com UG144 April 24, 2009...

  • Page 90: Access Without The Management Interface

    ‘0,’ the receiver will not pass frames longer Word 1” bit 30 than the maximum legal frame size specified in IEEE 802.3-2005. At ‘1,’ the receiver will not have an upper limit on frame size. www.xilinx.com 1-Gigabit Ethernet MAC v8.5 User Guide UG144 April 24, 2009...
  • Page 91 29 causes the GEMAC core to send a flow control frame out from the transmitter. When this bit is ‘0,’ asserting the pause_req signal will have no effect. 1-Gigabit Ethernet MAC v8.5 User Guide www.xilinx.com UG144 April 24, 2009...
  • Page 92 Configuration this bit is set to ‘1,’ the core will not mark Word 1” bit 24 control frames as ‘bad’ if they are greater than the minimum frame length. www.xilinx.com 1-Gigabit Ethernet MAC v8.5 User Guide UG144 April 24, 2009...

  • Page 93: Chapter 9: Constraining The Core

    Sections from this UCF are copied into the following descriptions to provide examples. These examples should be studied in conjunction with the HDL source code for the example design. 1-Gigabit Ethernet MAC v8.5 User Guide www.xilinx.com UG144 April 24, 2009...

  • Page 94: Chapter 9: Constraining The Core

    To prevent this logic being over constrained by the host_clk period, the relevant flip-flops for the MDIO logic can be grouped together and removed from the host_clk period constraint. This is shown in the previous UCF syntax for host_clk www.xilinx.com 1-Gigabit Ethernet MAC v8.5 User Guide UG144 April 24, 2009...

  • Page 95: Flow Control

    TNM="config_to_rx"; INST "*gmac_core/BU2/U0/MANIFGEN?MANAGEN/CONF/RX1_OUT*" TNM="config_to_rx"; INST "*gmac_core/BU2/U0/MANIFGEN?MANAGEN/CONF/FC_OUT_29" TNM="config_to_rx"; TIMESPEC "TS_config_to_rx" = FROM "config_to_rx" TO "rx_clock" TIG; INST "*gmac_core/BU2/U0/MANIFGEN?MANAGEN/CONF/TX_OUT*" TNM="config_to_tx"; INST "*gmac_core/BU2/U0/MANIFGEN?MANAGEN/CONF/FC_OUT_30" TNM="config_to_tx"; TIMESPEC "TS_config_to_tx" = FROM "config_to_tx" TO "tx_clock" TIG; 1-Gigabit Ethernet MAC v8.5 User Guide www.xilinx.com UG144 April 24, 2009...

  • Page 96: Constraints When Implementing An External Gmii

    In addition, the example design provides pad locking on the GMII for several families. This is a provided as a guideline only; there are no specific I/O location constraints for this core. www.xilinx.com 1-Gigabit Ethernet MAC v8.5 User Guide UG144 April 24, 2009...

  • Page 97: Figure 9-1: Input Gmii Timing

    Spartan-3A, and Virtex-4 devices. Phase-shifting is then applied to the DCM to align the resultant clock so that it will correctly sample the 2 ns GMII data valid window at the input flip-flops. 1-Gigabit Ethernet MAC v8.5 User Guide www.xilinx.com UG144 April 24, 2009...
  • Page 98 The following constraints are provided in the example design to link the instance of the IDELAYCTRL to the IODELAY components used on the GMII. These constraints aid the Xilinx tools in automatic IDELAYCTRL placement: # Group IODELAY and IDELAYCTRL components to aid placement INST "*gemac_block/gmii_interface/delay_gmii_rx_clk"...

  • Page 99: Understanding Timing Reports For Gmii Setup/Hold Timing

    1.962 ns of setup—this is less than the 2 ns required, so there is slack. The implementation requires –0.008 ns of hold—this is less than the 0 ns required, so there is slack. 1-Gigabit Ethernet MAC v8.5 User Guide www.xilinx.com UG144 April 24, 2009...
  • Page 100 1.866 ns relative to the following rising edge of the clock (since the IDELAY has acted to delay the clock by an entire period when measured from the input flip-flop). This is less than the 2 ns required, so there is slack. www.xilinx.com 1-Gigabit Ethernet MAC v8.5 User Guide UG144 April 24, 2009...

  • Page 101: Constraints When Implementing An External Rgmii

    IOB = true; INST "*rgmii_interface/rgmii_rx_ctl_ddr" IOB = true; # Inband Status Registers: place registers in IOB INST "*rgmii_interface/link_status" IOB = true; INST "*rgmii_interface/clock_speed*" IOB = true; INST "*rgmii_interface/duplex_status" IOB = true; 1-Gigabit Ethernet MAC v8.5 User Guide www.xilinx.com UG144 April 24, 2009...

  • Page 102: Figure 9-3: Input Rgmii Timing

    (though, if failing, the tools are NOT capable of fixing them: meeting these constraints is a manual process - see the following family specific sections for details): www.xilinx.com 1-Gigabit Ethernet MAC v8.5 User Guide UG144 April 24, 2009...
  • Page 103 The following constraint shows an example of setting the delay value for two of these IODELAY components. Data/Control bits can be adjusted individually to compensate for any PCB routing skew, if desired. 1-Gigabit Ethernet MAC v8.5 User Guide www.xilinx.com UG144 April 24, 2009...
  • Page 104 The following constraints are provided in the example design to link the instance of the IDELAYCTRL to the IODELAY components used on the RGMII. These constraints aid the Xilinx tools in automatic IDELAYCTRL placement: # Group IODELAY and IDELAYCTRL components to aid placement INST "*gemac_block/rgmii_interface/delay_rgmii_rx_clk"HIODELAY_GROUP =...

  • Page 105: Understanding Timing Reports For Rgmii Setup/Hold Timing

    1 ns required, so there is slack. The implementation requires 0.946 ns of hold to the –ve edge and 0.972 ns to the +ve edge. This is less than the 1 ns required, so there is slack. 1-Gigabit Ethernet MAC v8.5 User Guide www.xilinx.com UG144 April 24, 2009...
  • Page 106 0.821 ns relative to the following rising edge of the clock (since the IDELAY has acted to delay the clock by an entire period when measured from the input flip-flop). www.xilinx.com 1-Gigabit Ethernet MAC v8.5 User Guide UG144 April 24, 2009...

  • Page 107: Figure 9-4: Timing Report Setup/Hold Illustration

    12 ns -11.179 ns 12 ns 12.893 ns = 12.893 - 12 HOLD = 0.893 ns = 12 - 11.179 SETUP = 0.821 ns Figure 9-4: Timing Report Setup/Hold Illustration 1-Gigabit Ethernet MAC v8.5 User Guide www.xilinx.com UG144 April 24, 2009...
  • Page 108 -- DISCONTINUED PRODUCT -- Chapter 9: Constraining the Core www.xilinx.com 1-Gigabit Ethernet MAC v8.5 User Guide UG144 April 24, 2009...

  • Page 109: Chapter 10: Clocking And Resetting

    GMII setup and hold requirements (see “Spartan-3, Spartan- 3E, Spartan-3A and Virtex-4 Devices.”) 1-Gigabit Ethernet MAC BUFG IBUFG IBUFG BUFG gtx_clk gtx_clk gmii_rx_clk gmii_rx_clk Figure 10-1: Clock Management Logic with External GMII 1-Gigabit Ethernet MAC v8.5 User Guide www.xilinx.com UG144 April 24, 2009...

  • Page 110: With Rgmii

    PHY attached to the other end of the GMII. As illustrated in Figure 10-3, this results in a separate receiver clock domain for each core. www.xilinx.com 1-Gigabit Ethernet MAC v8.5 User Guide UG144 April 24, 2009...

  • Page 111: With Rgmii

    10-4. This results in a separate receiver clock domain for each core. Note: Although not illustrated, if the optional Management Interface is used, host_clk can also be shared between cores. 1-Gigabit Ethernet MAC v8.5 User Guide www.xilinx.com UG144 April 24, 2009...

  • Page 112: Reset Conditions

    Figure 10-5. This circuit provides controllable skews on the reset nets within the design. reset Configuration reset Core Registers Clock Figure 10-5: Reset Circuit for a Single Clock/reset Domain www.xilinx.com 1-Gigabit Ethernet MAC v8.5 User Guide UG144 April 24, 2009...

  • Page 113: Chapter 11: Interfacing To Other Cores

    PCS/PMA or SGMII core and instructions for obtaining the IP Update can be found on the Ethernet 1000BASE-X PCS/PMA or SGMII product page. A full description of the Ethernet 1000BASE-X PCS/PMA or SGMII core is outside the scope of this document. 1-Gigabit Ethernet MAC v8.5 User Guide www.xilinx.com UG144 April 24, 2009...

  • Page 114: Integration To Provide 1000Base-X Pcs With Tbi

    Figure 11-1: 1-Gigabit Ethernet MAC Extended to Include 1000BASE-X PCS with TBI www.xilinx.com 1-Gigabit Ethernet MAC v8.5 User Guide UG144 April 24, 2009...

  • Page 115: Integration To Provide 1000Base-X Pcs And Pma Using A Rocketio Transceiver

    RocketIO I/F mdio_in mdio_in mdio_out mdio_out mdio_tri mdio_tri connection Figure 11-2: 1-Gigabit Ethernet MAC Extended to Include 1000BASE-X PCS and PMA using a RocketIO Transceiver 1-Gigabit Ethernet MAC v8.5 User Guide www.xilinx.com UG144 April 24, 2009...
  • Page 116 GEMAC core now operate in the same clock domain. This allows clock crossing constraints between the gtx_clk and gmii_rx_clk clock domains to be removed from the GEMAC UCF. See “Timespecs for Critical Logic within the Core.” www.xilinx.com 1-Gigabit Ethernet MAC v8.5 User Guide UG144 April 24, 2009...

  • Page 117: Using A Rocketio Transceiver

    MDIO port can be connected to that of the Ethernet 1000BASE-X PCS/PMA or SGMII core to access its embedded configuration and status registers. See “Using the Optional Management Interface.” 1-Gigabit Ethernet MAC v8.5 User Guide www.xilinx.com UG144 April 24, 2009...

  • Page 118: Using The Rocketio Transceiver

    RocketIO I/F mdio_in mdio_in mdio_out mdio_out mdio_tri mdio_tri connection Figure 11-4: 1-Gigabit Ethernet MAC Extended to Include 1000BASE-X PCS and PMA using the RocketIO transceiver www.xilinx.com 1-Gigabit Ethernet MAC v8.5 User Guide UG144 April 24, 2009...

  • Page 119: Integration To Provide Sgmii Functionality

    Ethernet Statistics core takes in the tx_statistics_vector and rx_statistics_vector as inputs. Statistics values gathered can then be read out through the Statistics core Management Interface, that can be shared with the MAC Management Interface. 1-Gigabit Ethernet MAC v8.5 User Guide www.xilinx.com UG144 April 24, 2009...

  • Page 120: Figure 11-5: Interfacing The Ethernet Statistics To The 1-Gigabit Ethernet Mac

    Figure 11-5: Interfacing the Ethernet Statistics to the 1-Gigabit Ethernet MAC www.xilinx.com 1-Gigabit Ethernet MAC v8.5 User Guide UG144 April 24, 2009...
  • Page 121 (as illustrated in Figure 11-5). Table 11-1: Management Interface Transaction Types Transaction host_miim_sel host_addr[9] Configuration MIIM access Statistics Read 1-Gigabit Ethernet MAC v8.5 User Guide www.xilinx.com UG144 April 24, 2009...
  • Page 122 -- DISCONTINUED PRODUCT -- Chapter 11: Interfacing to Other Cores www.xilinx.com 1-Gigabit Ethernet MAC v8.5 User Guide UG144 April 24, 2009...

  • Page 123: Chapter 12: Implementing Your Design

    Using the Simulation Model For information about setting up your simulator to use the pre-implemented model, see the Xilinx Synthesis and Verification Design Guide, included in your Xilinx software installation. The unit delay structural model of the GEMAC core can be found in the CORE Generator project directory.

  • Page 124: Xst-Verilog

    Implementation Generating the Xilinx Netlist To generate the Xilinx netlist, the ngdbuild tools are used to translate and merge the individual design netlists into a single design database, the NGD file. Also merged at this stage is the UCF for the design.

  • Page 125: Placing-And-Routing The Design

    Run the netgen command to generate a chip-level simulation netlist for your design. VHDL $ netgen -sim -ofmt vhdl -ngm top_level_module_name_map.ngm \ -tm netlist top_level_module_name.ncd \ top_level_module_name_postimp.vhd Verilog $ netgen -sim -ofmt verilog -ngm top_level_module_name_map.ngm \ -tm netlist top_level_module_name.ncd \ top_level_module_name_postimp.v 1-Gigabit Ethernet MAC v8.5 User Guide www.xilinx.com UG144 April 24, 2009...

  • Page 126: Using The Model

    Chapter 12: Implementing Your Design Using the Model For information about setting up your simulator to use the pre-implemented model, see the Xilinx Synthesis and Verification Design Guide included in your Xilinx software installation. Other Implementation Information For more information about using the Xilinx implementation tool flow, including command line switches and options, see the Xilinx ISE®...

  • Page 127: Appendix A: Using The Client-Side Fifo

    The 10 Mbps/100 Mbps/1 Gbps Ethernet FIFO consists of independent transmit and receive FIFOs embedded in a top-level wrapper. Figure A-1 shows how the FIFO fits into a typical implementation. LocalLink Interface Client Interface GMII/RGMII Xilinx FPGA 10 Mbps, 1-Gigabit Ethernet MAC 100 Mbps, Core 1 Gbps Ethernet FIFO 1000BASE-T...

  • Page 128: Interfaces

    Source ready indicator tx_ll_dst_rdy_out_n Output tx_ll_clock Destination ready indicator tx_fifo_status[3:0] Output tx_ll_clock FIFO memory status tx_overflow Output tx_ll_clock Overflow signal indicates when a frame has been dropped in the FIFO www.xilinx.com 1-Gigabit Ethernet MAC v8.5 User Guide UG144 April 24, 2009...

  • Page 129: Receive Fifo

    Start of frame indicator rx_ll_eof_out_n Output rx_ll_clock End of frame indicator rx_ll_src_rdy_out_n Output rx_ll_clock Source ready indicator rx_ll_dst_rdy_in_n Input rx_ll_clock Destination ready indicator rx_fifo_status[3:0] Output rx_ll_clock FIFO memory status 1-Gigabit Ethernet MAC v8.5 User Guide www.xilinx.com UG144 April 24, 2009...

  • Page 130: Overview Of Locallink Interface

    Only when these signals are asserted simultaneously is data transferred from source to destination. The individual packet boundaries are marked by the sof_n and eof_n signals. For more information on the LocalLink interface see to Xilinx Application Note XAPP691, “Parameterizable LocalLink FIFO” available at direct.xilinx.com/bvdocs/appnotes/xapp691.pdf.

  • Page 131: Functional Operation

    The generic FULL_DUPLEX_ONLY is provided to allow the removal of logic and performance constraints necessary for half-duplex operation when using with the Xilinx Tri-Mode Ethernet MAC core. This generic can always be set to true when the FIFO is used with the GEMAC.

  • Page 132: Expanding Maximum Frame Size

    Conversion of the user interface 8 bit data path to a 16, 32, 64 or 128 bit data path can be made by connecting the LocalLink interface directly to the Parameterizable LocalLink FIFO, Xilinx Application Note XAPP691, Parameterizable LocalLink FIFO found at direct.xilinx.com/bvdocs/appnotes/xapp691.pdf.

  • Page 133: Appendix B: Core Verification, Compliance, And Interoperability

    Address Filtering Hardware Verification The GEMAC core has been tested in a variety of hardware test platforms at Xilinx to include a variety of parameterizations, including the following. The core has been tested with the Ethernet 1000BASE-X PCS/PMA or SGMII core from Xilinx.
  • Page 134 -- DISCONTINUED PRODUCT -- Appendix B: Core Verification, Compliance, and Interoperability www.xilinx.com 1-Gigabit Ethernet MAC v8.5 User Guide UG144 April 24, 2009...

  • Page 135: Appendix C: Calculating Dcm Phase-Shifting

    System Margin (ps) = UI(ps) * (working phase-shift range/128) Finding the Ideal Phase-Shift Xilinx cannot recommend a singular phase-shift value that is effective across all hardware platforms, and does not recommend attempting to determine the phase-shift setting empirically. In addition to the clock-to-data phase relationship, other factors such as...
  • Page 136 Once the range is determined, choose the average of the high and low working phase-shift values as the default. During the production test, Xilinx recommends that you re-examine the working range at corner case operating conditions to determine whether any final adjustments to the final phase-shift setting are needed.

  • Page 137: Appendix D: Core Latency

    9 clock periods of gmii_rx_clk. 1-Gigabit Ethernet MAC v8.5 User Guide www.xilinx.com UG144 April 24, 2009...
  • Page 138 -- DISCONTINUED PRODUCT -- Appendix D: Core Latency www.xilinx.com 1-Gigabit Ethernet MAC v8.5 User Guide UG144 April 24, 2009...

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