Interface Debug - Xilinx CAN FD v2.0 Product Manual

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Action: Ensure the following for proper inter-operation. All CAN FD nodes in the
network must be programmed to have the following:
a. Same Arbitration Phase bit rate
b. Same Data Phase bit rate
c. Same Arbitration Phase Sample Point Position
d. Same Data Phase Sample Point Position
Requirements (c) and (d) come from the fact that CAN FD nodes perform bit rate
switching at the respective sample point. For more information on the CAN FD protocol
and other recommendations, see the standard specification and other white paper
references in the
If any of the listed requirements are not met, various frame errors can be seen when
performing the CAN FD communication.

Interface Debug

AXI4-Lite Interfaces
Read from a register that does not have all 0s as a default to verify that the interface is
functional. See
Signals are compliant with AXI4-Lite protocol. The timing shown in
Note:
an example, and delays are not guaranteed to be the same as shown in the figure.
X-Ref Target - Figure C-1
CAN FD v2.0
PG223 December 5, 2018
References, page
Figure C-1
for a read timing diagram.
Figure C-1: AXI4-Lite Interface Read Timing Diagram
www.xilinx.com
97.
Appendix C: Debugging
Figure C-1
is provided as
94
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