Xilinx MicroBlaze Reference Manual page 151

Values for access permissions, memory types, quality of service and shareability domain are
defined in the following table.
Table 3-6: AXI Interface Signal Definitions
Interface
M_AXI_IP C_M_AXI_IP_ARPROT
M_AXI_DP C_M_AXI_DP_ARCACHE
C_M_AXI_DP_AWCACHE
C_M_AXI_DP_ARPROT
C_M_AXI_DP_AWPROT
C_M_AXI_DP_ARQOS
C_M_AXI_DP_AWQOS
M_AXI_IC C_M_AXI_IC_ARCACHE
M_ACE_IC C_M_AXI_IC_ARCACHE
C_M_AXI_IC_ARDOMAIN
M_AXI_IC C_M_AXI_IC_ARPROT
M_ACE_IC
C_M_AXI_IC_ARQOS
M_AXI_DC C_M_AXI_DC_ARCACHE
M_ACE_DC C_M_AXI_DC_ARCACHE
C_M_AXI_DC_ARDOMAIN
C_M_AXI_DC_AWDOMAIN
MicroBlaze Processor Reference Guide
UG984 (v2018.2) June 21, 2018
Chapter 3: MicroBlaze Signal Interface Description
Signal
Access Permission:
• Unprivileged, secure instruction access (100) if input signal
Non_Secure[1] = 0
• Unprivileged, non-secure instruction access (110) if input
signal Non_Secure[1] = 1
Memory Type, AXI4 protocol:
• Normal Non-cacheable Bufferable (0011)
Access Permission, AXI4 and AXI4-Lite protocol:
• Unprivileged, secure data access (000) if input signal
Non_Secure[0] = 0
• Unprivileged, non-secure data access (010) if input signal
Non_Secure[0] = 1
Quality of Service, AXI4 protocol:
• Priority 8 (1000)
Memory Type:
• Write-back Read and Write-allocate (1111)
Memory Type, normal access:
• Write-back Read and Write-allocate (1111)
Memory Type, DVM access:
• Normal Non-cacheable Non-bufferable (0010)
Shareability Domain:
• Inner shareable (01)
Access Permission:
• Unprivileged, secure instruction access (100) if input signal
Non_Secure[3] = 0
• Unprivileged, non-secure instruction access (110) if input
signal Non_Secure[3] = 1
Quality of Service:
• Priority 7 (0111)
Memory Type, normal access:
• Write-back Read and Write-allocate (1111)
Memory Type, exclusive access:
• Normal Non-cacheable Non-bufferable (0010)
Memory Type, normal and exclusive access:
• Write-back Read and Write-allocate (1111)
Memory Type, DVM access:
• Normal Non-cacheable Non-bufferable (0010)
Shareability Domain:
• Inner shareable (01)
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