Xilinx MicroBlaze Reference Manual page 245

Pseudocode
if EA = 1 then
← (
Addr rA) & (rB)
else
←
Addr (rA) + (rB)
if TLB_Miss(Addr) and MSR[VM] = 1 then
←
ESR[EC] 10010;ESR[S]
←
MSR[UMS]
else if Access_Protected(Addr) and MSR[UM] = 1 and MSR[VM] = 1 then
←
ESR[EC]
←
MSR[UMS]
else if Addr[31]
←
ESR[EC]
else if (VM = 0 and R = 1) or
(VM = 1 and R = 1 and E = 1) or
(VM = 1 and R = 0 and E = 0) then
(rD)[16:23]
else
(rD)[16:23]
Registers Altered
• rD, unless an exception is generated, in which case the register is unchanged
• MSR[UM], MSR[VM], MSR[UMS], MSR[VMS], if an exception is generated
• ESR[EC], ESR[S], if an exception is generated
• ESR[DIZ], if a data storage exception is generated
• ESR[W], ESR[Rx], if an unaligned data access exception is generated
Latency
• 1 cycle with
• 2 cycles with
Notes
The halfword reversed instruction is only valid if MicroBlaze is configured to use reorder instructions
(C_USE_REORDER_INSTR = 1).
The extended address instruction is only valid if MicroBlaze is configured to use extended address
(C_ADDR_SIZE > 32).
MicroBlaze Processor Reference Guide
UG984 (v2018.2) June 21, 2018
←
0
←
MSR[UM]; MSR[VMS]
←
10000;ESR[S] 0; ESR[DIZ]
←
MSR[UM]; MSR[VMS]
≠
0 then
←
00001; ESR[W] 0; ESR[S]
←
Mem(Addr); (rD)[24:31]
←
Mem(Addr+1); (rD)[24:31]
=0 or 2
C_AREA_OPTIMIZED
=1
C_AREA_OPTIMIZED
www.xilinx.com
Chapter 5: MicroBlaze Instruction Set Architecture
←
MSR[VM]; MSR[UM] 0; MSR[VM]
←
1
←
MSR[VM]; MSR[UM] 0; MSR[VM]
← ←
0; ESR[Rx]
←
Mem(Addr+1); (rD)[0:15]
←
Mem(Addr); (rD)[0:15]
←
0
←
0
rD
←
0
←
0
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