Xilinx MicroBlaze Reference Manual page 146

Instead of implementing the clock control with IP cores, an RTL Module can be used. A
possible VHDL implementation corresponding to Clock Control in the block diagram in
Figure 3-1 is given here. See the Vivado Design Suite User Guide: Designing IP Subsystems
Using IP Integrator (UG994)
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library UNISIM;
use UNISIM.VComponents.all;
entity clock_control is
port (
clkin
reset
sleep
interrupt
dbg_wakeup : in
clkout
);
end clock_control;
architecture Behavioral of clock_control is
attribute X_INTERFACE_INFO : string;
attribute X_INTERFACE_INFO of clkin : signal is "xilinx.com:signal:clock:1.0 clk CLK";
attribute X_INTERFACE_INFO of reset : signal is "xilinx.com:signal:reset:1.0 reset RST";
attribute X_INTERFACE_INFO of interrupt : signal
attribute X_INTERFACE_INFO of clkout : signal is "xilinx.com:signal:clock:1.0 clk_out CLK";
attribute X_INTERFACE_PARAMETER : string;
attribute X_INTERFACE_PARAMETER of reset
attribute X_INTERFACE_PARAMETER of interrupt : signal is "SENSITIVITY LEVEL_HIGH";
attribute X_INTERFACE_PARAMETER of clkout
signal clk_enable : std_logic := '1';
begin
clock_enable_dff : process (clkin) is
begin
if clkin'event and clkin = '1' then
if reset = '1' then
clk_enable <= '1';
elsif sleep = '1' and interrupt = '0' and dbg_wakeup = '0' then
clk_enable <= '0';
elsif clk_enable = '0' then
clk_enable <= '1';
end if;
end if;
end process clock_enable_dff;
clock_enable : component BUFGCE
port map (
O => clkout,
CE => clk_enable,
I => clkin
);
end Behavioral;
MicroBlaze Processor Reference Guide
UG984 (v2018.2) June 21, 2018
[Ref 12] for more information on RTL Modules.
: in std_logic;
: in std_logic;
: in std_logic;
: in std_logic;
std_logic;
: out std_logic
is "xilinx.com:signal:interrupt:1.0 interrupt INTERRUPT";
www.xilinx.com
Chapter 3: MicroBlaze Signal Interface Description
: signal is "POLARITY ACTIVE_HIGH";
: signal is "FREQ_HZ 100000000";
147
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