Xilinx MicroBlaze Reference Manual page 131

Both interfaces issue the following subset of the possible Distributed Virtual Memory
(DVM) transactions:
• DVM Operation
TLB Invalidate: Hypervisor TLB Invalidate by VA
-
Branch Predictor Invalidate: L Branch Predictor Invalidate all
-
Physical Instruction Cache Invalidate: Non-secure Physical Instruction Cache
-
Invalidate by PA without Virtual Index
Virtual Instruction Cache Invalidate: Hypervisor Invalidate by VA
-
• DVM Sync
Synchronization
-
• DVM Complete
In addition to the DVM transactions above, the interfaces only accept the
-
CleanInvalid
the instruction cache, and invalidate the indicated data cache lines. If any other
transactions are received, the behavior is undefined.
Only a subset of AXI4 transactions are utilized by the interfaces, as described in
-
Cache Interfaces.
MicroBlaze Processor Reference Guide
UG984 (v2018.2) June 21, 2018
and transactions. These transactions have no effect in
MakeInvalid
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Chapter 2: MicroBlaze Architecture
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