Xilinx MicroBlaze Reference Manual page 259

mul Multiply
rD, rA, rB
mul
0 1 0 0 0 0
0
6
Description
Multiplies the contents of registers rA and rB and puts the result in register rD. This is a 32-bit by 32-
bit multiplication that will produce a 64-bit result. The least significant word of this value is placed in
rD. The most significant word is discarded.
Pseudocode
←
(rD) LSW( (rA)
Registers Altered
• rD
Latency
• 1 cycle with
• 3 cycles with
Note
This instruction is only valid if the target architecture has multiplier primitives, and if present, the
MicroBlaze parameter C_USE_HW_MUL is greater than 0.
MicroBlaze Processor Reference Guide
UG984 (v2018.2) June 21, 2018
rD rA
11
×
(rB) )
=0 or 2
C_AREA_OPTIMIZED
=1
C_AREA_OPTIMIZED
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Chapter 5: MicroBlaze Instruction Set Architecture
rB 0 0 0 0 0 0 0 0 0 0 0
16 21 31
260
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