Xilinx MicroBlaze Reference Manual page 21

Table 2-6: MicroBlaze Instruction Set Summary (Cont'd)
Type A
Type B
LWEA Rd,Ra,Rb 110010
SB Rd,Ra,Rb 110100
SBR Rd,Ra,Rb
SBEA Rd,Ra,Rb 110100
SH Rd,Ra,Rb 110101
SHR Rd,Ra,Rb
SHEA Rd,Ra,Rb 110101
SW Rd,Ra,Rb 110110
SWR Rd,Ra,Rb
SWX Rd,Ra,Rb 110110
SWEA Rd,Ra,Rb 110110
LBUI Rd,Ra,Imm 111000
LHUI Rd,Ra,Imm 111001
LWI Rd,Ra,Imm 111010
SBI Rd,Ra,Imm 111100
SHI Rd,Ra,Imm 111101
SWI Rd,Ra,Imm 111110
1. Due to the many different corner cases involved in floating-point arithmetic, only the normal behavior is described. A full
description of the behavior can be found in
MicroBlaze Processor Reference Guide
UG984 (v2018.2) June 21, 2018
0-5 6-10 11-15 16-20
0-5 6-10 11-15
Rd Ra
Rd Ra
Rd Ra
Rd Ra
Rd Ra
Rd Ra
Rd Ra
Rd Ra
Rd Ra
Rd Ra
Rd Ra
Rd Ra
Rd Ra
Rd Ra
Chapter 5, "MicroBlaze Instruction Set Architecture."
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Chapter 2: MicroBlaze Architecture
21-31
16-31
Rb 00010000000 Addr := Ra & Rb
Rd := *Addr
Rb 00000000000 Addr := Ra + Rb
01000000000 *Addr[0:8] := Rd[24:31]
Rb 00010000000 Addr := Ra & Rb
*Addr[0:8] := Rd[24:31]
Rb 00000000000 Addr := Ra + Rb
01000000000 *Addr[0:16] := Rd[16:31]
Rb 00010000000 Addr := Ra & Rb
*Addr[0:16] := Rd[16:31]
Rb 00000000000 Addr := Ra + Rb
01000000000
*Addr := Rd
Rb 10000000000 Addr := Ra + Rb
*Addr := Rd if Reservation = 1
Reservation := 0
Rb 00010000000 Addr := Ra & Rb
*Addr := Rd
Imm Addr := Ra + s(Imm)
Rd[0:23] := 0
Rd[24:31] := *Addr[0:7]
Imm Addr := Ra + s(Imm)
Rd[0:15] := 0
Rd[16:31] := *Addr[0:15]
Imm Addr := Ra + s(Imm)
Rd := *Addr
Imm Addr := Ra + s(Imm)
*Addr[0:7] := Rd[24:31]
Imm Addr := Ra + s(Imm)
*Addr[0:15] := Rd[16:31]
Imm Addr := Ra + s(Imm)
*Addr := Rd
Semantics
21
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